Module Name: src
Committed By: jmcneill
Date: Fri Nov 28 15:29:48 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h
Log Message:
add mixer processor regs
To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.54 src/sys/arch/arm/allwinner/awin_reg.h:1.55
--- src/sys/arch/arm/allwinner/awin_reg.h:1.54 Tue Nov 25 00:06:32 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Fri Nov 28 15:29:48 2014
@@ -2002,6 +2002,220 @@ struct awin_mmc_idma_descriptor {
#define AWIN_HDMI_DDC_CLOCK_M __BITS(6,3)
#define AWIN_HDMI_DDC_CLOCK_N __BITS(2,0)
+/* Mixer processor */
+#define AWIN_MP_CTL_REG 0x0000
+#define AWIN_MP_STS_REG 0x0004
+#define AWIN_MP_IDMAGBLCTL_REG 0x0008
+#define AWIN_MP_IDMA_H4ADD_REG 0x000C
+#define AWIN_MP_IDMA_L32ADD_REG(n) (0x0010 + ((n) * 4))
+#define AWIN_MP_IDMALINEWIDTH_REG(n) (0x0020 + ((n) * 4))
+#define AWIN_MP_IDMASIZE_REG(n) (0x0030 + ((n) * 4))
+#define AWIN_MP_IDMACOOR_REG(n) (0x0040 + ((n) * 4))
+#define AWIN_MP_IDMASET_REG(n) (0x0050 + ((n) * 4))
+#define AWIN_MP_IDMAFILLCOLOR_REG(n) (0x0060 + ((n) * 4))
+#define AWIN_MP_CSC0CTL_REG 0x0074
+#define AWIN_MP_CSC1CTL_REG 0x0078
+#define AWIN_MP_SCACTL_REG 0x0080
+#define AWIN_MP_SCAOUTSIZE_REG 0x0084
+#define AWIN_MP_SCAHORFCT_REG 0x0088
+#define AWIN_MP_SCAVERFCT_REG 0x008c
+#define AWIN_MP_SCAHORPHASE_REG 0x0090
+#define AWIN_MP_SCAVERPHASE_REG 0x0094
+#define AWIN_MP_ROPCTL_REG 0x00b0
+#define AWIN_MP_ROPIDX0CTL_REG 0x00b8
+#define AWIN_MP_ROPIDX1CTL_REG 0x00bc
+#define AWIN_MP_ALPHACKCTL_REG 0x00c0
+#define AWIN_MP_CKMIN_REG 0x00c4
+#define AWIN_MP_CKMAX_REG 0x00c8
+#define AWIN_MP_ROPOUTFILLCOLOR_REG 0x00cc
+#define AWIN_MP_CSC2CTL_REG 0x00d0
+#define AWIN_MP_OUTCTL_REG 0x00e0
+#define AWIN_MP_OUTSIZE_REG 0x00e8
+#define AWIN_MP_OUTH4ADD_REG 0x00ec
+#define AWIN_MP_OUTL32ADD_REG(n) (0x00f0 + ((n) * 4))
+#define AWIN_MP_OUTLINEWIDTH_REG(n) (0x0100 + ((n) * 4))
+#define AWIN_MP_OUTALPHACTL_REG 0x0120
+#define AWIN_MP_MBCTL_REG(n) (0x0130 + ((n) * 4))
+#define AWIN_MP_CMDQUECTL_REG 0x0140
+#define AWIN_MP_CMDQUESTS_REG 0x0144
+#define AWIN_MP_CMDQUEADD_REG 0x0148
+#define AWIN_MP_ICSCYGCOEF_REG(n) (0x0180 + ((n) * 4))
+#define AWIN_MP_ICSCYGCONS_REG 0x018c
+#define AWIN_MP_ICSCCURCOEF_REG(n) (0x0190 + ((n) * 4))
+#define AWIN_MP_ICSCCURCONS_REG 0x019c
+#define AWIN_MP_ICSCVBCOEF_REG(n) (0x01a0 + ((n) * 4))
+#define AWIN_MP_ICSCVBCONS_REG 0x01ac
+#define AWIN_MP_OCSCYGCOEF_REG(n) (0x01c0 + ((n) * 4))
+#define AWIN_MP_OCSCYGCONS_REG 0x01cc
+#define AWIN_MP_OCSCCURCOEF_REG(n) (0x01d0 + ((n) * 4))
+#define AWIN_MP_OCSCCURCONS_REG 0x01dc
+#define AWIN_MP_OCSCVBCOEF_REG(n) (0x01e0 + ((n) * 4))
+#define AWIN_MP_OCSCVBCONS_REG 0x01ec
+#define AWIN_MP_SCAL_HORIZ_FILT_BLOCK 0x0200
+#define AWIN_MP_SCAL_VERT_FILT_BLOCK 0x0280
+#define AWIN_MP_PALETTE_TABLE 0x0400
+
+#define AWIN_MP_CTL_HWERRIRQ_EN __BIT(9)
+#define AWIN_MP_CTL_FINISHIRQ_EN __BIT(8)
+#define AWIN_MP_CTL_START_CTL __BIT(1)
+#define AWIN_MP_CTL_MP_EN __BIT(0)
+
+#define AWIN_MP_STS_HWERR_FLAG __BIT(13)
+#define AWIN_MP_STS_BUSY_FLAG __BIT(12)
+#define AWIN_MP_STS_HWERRIRQ_FLAG __BIT(9)
+#define AWIN_MP_STS_FINISHIRQ_FLAG __BIT(8)
+
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER __BITS(9,8)
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_TD_LR 0
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_TD_RL 1
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_DT_LR 2
+#define AWIN_MP_IDMAGLBCTL_MEMSCANORDER_DT_RL 3
+
+#define AWIN_MP_IDMA_H4ADD_IDMA3_H4ADD __BITS(27,24)
+#define AWIN_MP_IDMA_H4ADD_IDMA2_H4ADD __BITS(19,16)
+#define AWIN_MP_IDMA_H4ADD_IDMA1_H4ADD __BITS(11,8)
+#define AWIN_MP_IDMA_H4ADD_IDMA0_H4ADD __BITS(3,0)
+
+#define AWIN_MP_IDMASIZE_HEIGHT __BITS(28,16)
+#define AWIN_MP_IDMASIZE_WIDTH __BITS(12,0)
+
+#define AWIN_MP_IDMACOOR_YCOOR __BITS(31,16)
+#define AWIN_MP_IDMACOOR_XCOOR __BITS(15,0)
+
+#define AWIN_MP_IDMASET_IDMA_GLBALPHA __BITS(31,24)
+#define AWIN_MP_IDMASET_MBFMT __BIT(22)
+#define AWIN_MP_IDMASET_MBSIZE __BITS(21,20)
+#define AWIN_MP_IDMASET_MBSIZE_16X16 0
+#define AWIN_MP_IDMASET_MBSIZE_32X32 1
+#define AWIN_MP_IDMASET_MBSIZE_64X64 2
+#define AWIN_MP_IDMASET_MBSIZE_128X128 3
+#define AWIN_MP_IDMASET_IDMA_FCMODEN __BIT(16)
+#define AWIN_MP_IDMASET_IDMA_PS __BITS(15,12)
+#define AWIN_MP_IDMASET_IDMA_FMT __BITS(11,8)
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB888 0
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB444 1
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB155 2
+#define AWIN_MP_IDMASET_IDMA_FMT_RGB565 3
+#define AWIN_MP_IDMASET_IDMA_FMT_IYUV422 4
+#define AWIN_MP_IDMASET_IDMA_FMT_UV88 5
+#define AWIN_MP_IDMASET_IDMA_FMT_Y8 6
+#define AWIN_MP_IDMASET_IDMA_FMT_8BPP_MP 7
+#define AWIN_MP_IDMASET_IDMA_FMT_4BPP_MP 8
+#define AWIN_MP_IDMASET_IDMA_FMT_2BPP_MP 9
+#define AWIN_MP_IDMASET_IDMA_FMT_1BPP_MP 10
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL __BITS(7,4)
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_NORMAL 0
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_X 1
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_Y 2
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_XY 3
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_A 4
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_AX 5
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_AY 6
+#define AWIN_MP_IDMASET_IDMA_ROPMIRCTL_AXY 7
+#define AWIN_MP_IDMASET_IDMA_ALPHACTL __BITS(3,2)
+#define AWIN_MP_IDMASET_IDMA_WORKMOD __BIT(1)
+#define AWIN_MP_IDMASET_IDMA_EN __BIT(0)
+
+#define AWIN_MP_CSCxCTL_DATAMOD __BITS(7,4)
+#define AWIN_MP_CSCxCTL_EN __BIT(0)
+
+#define AWIN_MP_SCACTL_SCA_ALGSEL __BITS(5,4)
+#define AWIN_MP_SCACTL_SCA_EN __BIT(0)
+
+#define AWIN_MP_SCAOUTSIZE_OUTHEIGHT __BITS(28,16)
+#define AWIN_MP_SCAOUTSIZE_OUTWIDTH __BITS(12,0)
+
+#define AWIN_MP_SCAHORFCT_HORINTFCT __BITS(23,16)
+#define AWIN_MP_SCAHORFCT_HORFRAFCT __BITS(15,0)
+
+#define AWIN_MP_SCAVERFCT_VERINTFCT __BITS(23,16)
+#define AWIN_MP_SCAVERFCT_VERFRAFCT __BITS(15,0)
+
+#define AWIN_MP_SCAHORPHASE_HORPHASE __BITS(19,0)
+
+#define AWIN_MP_SCAVERPHASE_VERPHASE __BITS(19,0)
+
+#define AWIN_MP_ROPCTL_ROP_ALPHABYPASSSEL __BITS(15,14)
+#define AWIN_MP_ROPCTL_ROP_REDBYPASSSEL __BITS(13,12)
+#define AWIN_MP_ROPCTL_ROP_GREENBYPASSSEL __BITS(11,10)
+#define AWIN_MP_ROPCTL_ROP_BLUEBYPASSSEL __BITS(9,8)
+#define AWIN_MP_ROPCTL_ROP_ALPHABYPASSEN __BIT(7)
+#define AWIN_MP_ROPCTL_ROP_REDBYPASSEN __BIT(6)
+#define AWIN_MP_ROPCTL_ROP_GREENBYPASSEN __BIT(5)
+#define AWIN_MP_ROPCTL_ROP_BLUEBYPSASEN __BIT(4)
+#define AWIN_MP_ROPCTL_ROP_MOD __BIT(0)
+
+#define AWIN_MP_ROPIDXxCTL_CH2IGN_EN __BIT(18)
+#define AWIN_MP_ROPIDXxCTL_CH1IGN_EN __BIT(17)
+#define AWIN_MP_ROPIDXxCTL_CH0IGN_EN __BIT(16)
+#define AWIN_MP_ROPIDXxCTL_NOD7_CTL __BIT(15)
+#define AWIN_MP_ROPIDXxCTL_NOD6_CTL __BITS(14,11)
+#define AWIN_MP_ROPIDXxCTL_NOD5_CTL __BIT(10)
+#define AWIN_MP_ROPIDXxCTL_NOD4_CTL __BITS(9,6)
+#define AWIN_MP_ROPIDXxCTL_NOD3_CTL __BIT(5)
+#define AWIN_MP_ROPIDXxCTL_NOD2_CTL __BIT(4)
+#define AWIN_MP_ROPIDXxCTL_NOD1_CTL __BIT(3)
+#define AWIN_MP_ROPIDXxCTL_NOD0_CTL __BITS(2,0)
+
+#define AWIN_MP_ALPHACKCTL_CH3GALPHA __BITS(31,24)
+#define AWIN_MP_ALPHACKCTL_ROPGALPHA __BITS(23,16)
+#define AWIN_MP_ALPHACKCTL_CH3ALPHACTL __BITS(15,14)
+#define AWIN_MP_ALPHACKCTL_ROPALPHACTL __BITS(13,12)
+#define AWIN_MP_ALPHACKCTL_CK_REDCON __BIT(10)
+#define AWIN_MP_ALPHACKCTL_CK_GREENCON __BIT(9)
+#define AWIN_MP_ALPHACKCTL_CK_BLUECON __BIT(8)
+#define AWIN_MP_ALPHACKCTL_ICH3_PREMUL __BIT(7)
+#define AWIN_MP_ALPHACKCTL_IROP_PREMUL __BIT(6)
+#define AWIN_MP_ALPHACKCTL_O_PREMUL __BIT(5)
+#define AWIN_MP_ALPHACKCTL_PRI __BIT(4)
+#define AWIN_MP_ALPHACKCTL_ALPHACK_MOD __BITS(2,1)
+#define AWIN_MP_ALPHACKCTL_ALPHACK_EN __BIT(0)
+
+#define AWIN_MP_CSC2CTL_CSC2_EN __BIT(0)
+
+#define AWIN_MP_OUTCTL_OUT_PS __BITS(11,8)
+#define AWIN_MP_OUTCTL_RND_EN __BIT(7)
+#define AWIN_MP_OUTCTL_OUT_FMT __BITS(3,0)
+#define AWIN_MP_OUTCTL_OUT_FMT_ARGB8888 0
+#define AWIN_MP_OUTCTL_OUT_FMT_ARGB4444 1
+#define AWIN_MP_OUTCTL_OUT_FMT_ARGB1555 2
+#define AWIN_MP_OUTCTL_OUT_FMT_RGB565 3
+#define AWIN_MP_OUTCTL_OUT_FMT_IYUV422 4
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV422_UVC 5
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV422 6
+#define AWIN_MP_OUTCTL_OUT_FMT_8BPP_M 7
+#define AWIN_MP_OUTCTL_OUT_FMT_4BPP_M 8
+#define AWIN_MP_OUTCTL_OUT_FMT_2BPP_M 9
+#define AWIN_MP_OUTCTL_OUT_FMT_1BPP_M 10
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV420_UVC 11
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV420 12
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV411_UVC 13
+#define AWIN_MP_OUTCTL_OUT_FMT_YUV411 14
+
+#define AWIN_MP_OUTSIZE_OUT_HEIGHT __BITS(28,16)
+#define AWIN_MP_OUTSIZE_OUT_WIDTH __BITS(12,0)
+
+#define AWIN_MP_OUTH4ADD_OUTCH2_H4ADD __BITS(19,16)
+#define AWIN_MP_OUTH4ADD_OUTCH1_H4ADD __BITS(11,8)
+#define AWIN_MP_OUTH4ADD_OUTCH0_H4ADD __BITS(3,0)
+
+#define AWIN_MP_OUTALPHACTL_IMG_ALPHA __BITS(31,24)
+#define AWIN_MP_OUTALPHACTL_NONIMG_ALPHA __BITS(23,16)
+#define AWIN_MP_OUTALPHACTL_A2ALPHACTL __BITS(7,6)
+#define AWIN_MP_OUTALPHACTL_A3ALPHACTL __BITS(5,4)
+#define AWIN_MP_OUTALPHACTL_A1ALPHACTL __BITS(3,2)
+#define AWIN_MP_OUTALPHACTL_A0ALPHACTL __BITS(1,0)
+
+#define AWIN_MP_MBCTL_Y_OFFSET __BITS(31,16)
+#define AWIN_MP_MBCTL_X_OFFSET __BITS(15,0)
+
+#define AWIN_MP_CMDQUECTL_FINISHIRQ_EN __BIT(8)
+#define AWIN_MP_CMDQUECTL_START_CTL __BIT(1)
+#define AWIN_MP_CMDQUECTL_EN __BIT(0)
+
+#define AWIN_MP_CMDQUESTS_BUSY_FLAG __BIT(12)
+#define AWIN_MP_CMDQUESTS_FINISHIRQ_FLAG __BIT(8)
+
/*
* A31 registers
*/
