Module Name: src Committed By: jmcneill Date: Fri Oct 6 21:09:21 UTC 2017
Modified Files: src/sys/arch/arm/sunxi: files.sunxi sunxi_ccu.h sunxi_ccu_nkmp.c Added Files: src/sys/arch/arm/sunxi: sun4i_a10_ccu.c sun4i_a10_ccu.h sun7i_a20_ccu.h Log Message: Add driver for sun4i (A10) and sun7i (A20) clock controller. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/sunxi/files.sunxi cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sun4i_a10_ccu.c \ src/sys/arch/arm/sunxi/sun4i_a10_ccu.h \ src/sys/arch/arm/sunxi/sun7i_a20_ccu.h cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/sunxi/sunxi_ccu.h cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/sunxi/sunxi_ccu_nkmp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/sunxi/files.sunxi diff -u src/sys/arch/arm/sunxi/files.sunxi:1.26 src/sys/arch/arm/sunxi/files.sunxi:1.27 --- src/sys/arch/arm/sunxi/files.sunxi:1.26 Thu Oct 5 01:30:26 2017 +++ src/sys/arch/arm/sunxi/files.sunxi Fri Oct 6 21:09:21 2017 @@ -1,4 +1,4 @@ -# $NetBSD: files.sunxi,v 1.26 2017/10/05 01:30:26 jmcneill Exp $ +# $NetBSD: files.sunxi,v 1.27 2017/10/06 21:09:21 jmcneill Exp $ # # Configuration info for Allwinner sunxi family SoCs # @@ -28,6 +28,11 @@ file arch/arm/sunxi/sunxi_ccu_nkmp.c su file arch/arm/sunxi/sunxi_ccu_phase.c sunxi_ccu file arch/arm/sunxi/sunxi_ccu_prediv.c sunxi_ccu +# CCU (A10/A20) +device sun4ia10ccu: sunxi_ccu +attach sun4ia10ccu at fdt with sunxi_a10_ccu +file arch/arm/sunxi/sun4i_a10_ccu.c sunxi_a10_ccu + # CCU (A13) device sun5ia13ccu: sunxi_ccu attach sun5ia13ccu at fdt with sunxi_a13_ccu Index: src/sys/arch/arm/sunxi/sunxi_ccu.h diff -u src/sys/arch/arm/sunxi/sunxi_ccu.h:1.12 src/sys/arch/arm/sunxi/sunxi_ccu.h:1.13 --- src/sys/arch/arm/sunxi/sunxi_ccu.h:1.12 Thu Oct 5 01:28:47 2017 +++ src/sys/arch/arm/sunxi/sunxi_ccu.h Fri Oct 6 21:09:21 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: sunxi_ccu.h,v 1.12 2017/10/05 01:28:47 jmcneill Exp $ */ +/* $NetBSD: sunxi_ccu.h,v 1.13 2017/10/06 21:09:21 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -107,10 +107,11 @@ struct sunxi_ccu_nkmp { uint32_t enable; uint32_t flags; const struct sunxi_ccu_nkmp_tbl *table; -#define SUNXI_CCU_NKMP_DIVIDE_BY_TWO __BIT(0) -#define SUNXI_CCU_NKMP_FACTOR_N_EXACT __BIT(1) -#define SUNXI_CCU_NKMP_SCALE_CLOCK __BIT(2) -#define SUNXI_CCU_NKMP_FACTOR_P_POW2 __BIT(3) +#define SUNXI_CCU_NKMP_DIVIDE_BY_TWO __BIT(0) +#define SUNXI_CCU_NKMP_FACTOR_N_EXACT __BIT(1) +#define SUNXI_CCU_NKMP_SCALE_CLOCK __BIT(2) +#define SUNXI_CCU_NKMP_FACTOR_P_POW2 __BIT(3) +#define SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE __BIT(4) }; int sunxi_ccu_nkmp_enable(struct sunxi_ccu_softc *, Index: src/sys/arch/arm/sunxi/sunxi_ccu_nkmp.c diff -u src/sys/arch/arm/sunxi/sunxi_ccu_nkmp.c:1.6 src/sys/arch/arm/sunxi/sunxi_ccu_nkmp.c:1.7 --- src/sys/arch/arm/sunxi/sunxi_ccu_nkmp.c:1.6 Sun Aug 13 19:18:08 2017 +++ src/sys/arch/arm/sunxi/sunxi_ccu_nkmp.c Fri Oct 6 21:09:21 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: sunxi_ccu_nkmp.c,v 1.6 2017/08/13 19:18:08 jmcneill Exp $ */ +/* $NetBSD: sunxi_ccu_nkmp.c,v 1.7 2017/10/06 21:09:21 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_nkmp.c,v 1.6 2017/08/13 19:18:08 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_nkmp.c,v 1.7 2017/10/06 21:09:21 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -114,6 +114,9 @@ sunxi_ccu_nkmp_get_rate(struct sunxi_ccu if ((nkmp->flags & SUNXI_CCU_NKMP_FACTOR_N_EXACT) == 0) n++; + if ((nkmp->flags & SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE) != 0 && n == 0) + n++; + k++; if ((nkmp->flags & SUNXI_CCU_NKMP_FACTOR_P_POW2) != 0) Added files: Index: src/sys/arch/arm/sunxi/sun4i_a10_ccu.c diff -u /dev/null src/sys/arch/arm/sunxi/sun4i_a10_ccu.c:1.1 --- /dev/null Fri Oct 6 21:09:21 2017 +++ src/sys/arch/arm/sunxi/sun4i_a10_ccu.c Fri Oct 6 21:09:21 2017 @@ -0,0 +1,408 @@ +/* $NetBSD: sun4i_a10_ccu.c,v 1.1 2017/10/06 21:09:21 jmcneill Exp $ */ + +/*- + * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> + +__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.1 2017/10/06 21:09:21 jmcneill Exp $"); + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/device.h> +#include <sys/systm.h> + +#include <dev/fdt/fdtvar.h> + +#include <arm/sunxi/sunxi_ccu.h> +#include <arm/sunxi/sun4i_a10_ccu.h> +#include <arm/sunxi/sun7i_a20_ccu.h> + +#define PLL1_CFG_REG 0x000 +#define PLL2_CFG_REG 0x008 +#define PLL6_CFG_REG 0x028 +#define OSC24M_CFG_REG 0x050 +#define CPU_AHB_APB0_CFG_REG 0x054 +#define APB1_CLK_DIV_REG 0x058 +#define AHB_GATING_REG0 0x060 +#define AHB_GATING_REG1 0x064 +#define APB0_GATING_REG 0x068 +#define APB1_GATING_REG 0x06c +#define SD0_SCLK_CFG_REG 0x088 +#define SD1_SCLK_CFG_REG 0x08c +#define SD2_SCLK_CFG_REG 0x090 +#define SD3_SCLK_CFG_REG 0x094 +#define USBPHY_CFG_REG 0x0cc +#define BE_CFG_REG 0x104 +#define FE_CFG_REG 0x10c +#define CSI_CFG_REG 0x134 +#define VE_CFG_REG 0x13c +#define AUDIO_CODEC_SCLK_CFG_REG 0x140 +#define MALI_CLOCK_CFG_REG 0x154 +#define IEP_SCLK_CFG_REG 0x160 + +static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); +static void sun4i_a10_ccu_attach(device_t, device_t, void *); + +enum sun4i_a10_ccu_type { + CCU_A10 = 1, + CCU_A20, +}; + +static const struct of_compat_data compat_data[] = { + { "allwinner,sun4i-a10-ccu", CCU_A10 }, + { "allwinner,sun7i-a20-ccu", CCU_A20 }, + { NULL } +}; + +CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), + sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); + +static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { + SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), + SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), + SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), +}; + +static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; +static const char *axi_parents[] = { "cpu" }; +static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; +static const char *apb0_parents[] = { "ahb" }; +static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; +static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" }; + +static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { + { 24576000, 86, 0, 21, 3 }, + { 0 } +}; + +static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { + SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", + OSC24M_CFG_REG, 0), + + SUNXI_CCU_NKMP(A10_CLK_PLL_CORE, "pll_core", "osc24m", + PLL1_CFG_REG, /* reg */ + __BITS(12,8), /* n */ + __BITS(5,4), /* k */ + __BITS(1,0), /* m */ + __BITS(17,16), /* p */ + __BIT(31), /* enable */ + SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | + SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE), + + SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", + PLL2_CFG_REG, /* reg */ + __BITS(14,8), /* n */ + 0, /* k */ + __BITS(4,0), /* m */ + __BITS(29,26), /* p */ + __BIT(31), /* enable */ + 0, /* lock */ + sun4i_a10_ac_dig_table, /* table */ + 0), + + SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", + PLL6_CFG_REG, /* reg */ + __BITS(12,8), /* n */ + __BITS(5,4), /* k */ + 0, /* m */ + 0, /* p */ + __BIT(31), /* enable */ + SUNXI_CCU_NKMP_FACTOR_N_EXACT), + + SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", + 2, 1), + + SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", + PLL6_CFG_REG, /* reg */ + 0, /* n */ + 0, /* k */ + __BITS(1,0), /* m */ + 0, /* p */ + __BIT(14), /* enable */ + 0), + + SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, + CPU_AHB_APB0_CFG_REG, /* reg */ + 0, /* div */ + __BITS(17,16), /* sel */ + 0), + + SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, + CPU_AHB_APB0_CFG_REG, /* reg */ + __BITS(1,0), /* div */ + 0, /* sel */ + 0), + + SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, + CPU_AHB_APB0_CFG_REG, /* reg */ + __BITS(5,4), /* div */ + __BITS(7,6), /* sel */ + SUNXI_CCU_DIV_POWER_OF_TWO), + + SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, + CPU_AHB_APB0_CFG_REG, /* reg */ + __BITS(9,8), /* div */ + 0, /* sel */ + SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), + + SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, + APB1_CLK_DIV_REG, /* reg */ + __BITS(17,16), /* n */ + __BITS(4,0), /* m */ + __BITS(25,24), /* sel */ + 0, /* enable */ + SUNXI_CCU_NM_POWER_OF_TWO), + + SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, + SD0_SCLK_CFG_REG, /* reg */ + __BITS(17,16), /* n */ + __BITS(3,0), /* m */ + __BITS(25,24), /* sel */ + __BIT(31), /* enable */ + SUNXI_CCU_NM_POWER_OF_TWO), + SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, + SD1_SCLK_CFG_REG, /* reg */ + __BITS(17,16), /* n */ + __BITS(3,0), /* m */ + __BITS(25,24), /* sel */ + __BIT(31), /* enable */ + SUNXI_CCU_NM_POWER_OF_TWO), + SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, + SD2_SCLK_CFG_REG, /* reg */ + __BITS(17,16), /* n */ + __BITS(3,0), /* m */ + __BITS(25,24), /* sel */ + __BIT(31), /* enable */ + SUNXI_CCU_NM_POWER_OF_TWO), + SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, + SD3_SCLK_CFG_REG, /* reg */ + __BITS(17,16), /* n */ + __BITS(3,0), /* m */ + __BITS(25,24), /* sel */ + __BIT(31), /* enable */ + SUNXI_CCU_NM_POWER_OF_TWO), + + /* AHB_GATING_REG0 */ + SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", + AHB_GATING_REG0, 0), + SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", + AHB_GATING_REG0, 1), + SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", + AHB_GATING_REG0, 2), + SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", + AHB_GATING_REG0, 3), + SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", + AHB_GATING_REG0, 4), + SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", + AHB_GATING_REG0, 5), + SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", + AHB_GATING_REG0, 6), + SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", + AHB_GATING_REG0, 7), + SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", + AHB_GATING_REG0, 8), + SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", + AHB_GATING_REG0, 9), + SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", + AHB_GATING_REG0, 10), + SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", + AHB_GATING_REG0, 11), + SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", + AHB_GATING_REG0, 12), + SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", + AHB_GATING_REG0, 13), + SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", + AHB_GATING_REG0, 14), + SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", + AHB_GATING_REG0, 16), + SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", + AHB_GATING_REG0, 17), + SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", + AHB_GATING_REG0, 18), + SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", + AHB_GATING_REG0, 20), + SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", + AHB_GATING_REG0, 21), + SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", + AHB_GATING_REG0, 22), + SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", + AHB_GATING_REG0, 23), + SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", + AHB_GATING_REG0, 25), + SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", + AHB_GATING_REG0, 28), + + /* AHB_GATING_REG1. Missing: TVE, HDMI */ + SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", + AHB_GATING_REG1, 0), + SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", + AHB_GATING_REG1, 1), + SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", + AHB_GATING_REG1, 2), + SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", + AHB_GATING_REG1, 3), + SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", + AHB_GATING_REG1, 4), + SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", + AHB_GATING_REG1, 5), + SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", + AHB_GATING_REG1, 8), + SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", + AHB_GATING_REG1, 9), + SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", + AHB_GATING_REG1, 10), + SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", + AHB_GATING_REG1, 11), + SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", + AHB_GATING_REG1, 12), + SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", + AHB_GATING_REG1, 13), + SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", + AHB_GATING_REG1, 14), + SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", + AHB_GATING_REG1, 15), + SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", + AHB_GATING_REG1, 17), + SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", + AHB_GATING_REG1, 18), + SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", + AHB_GATING_REG1, 20), + + /* APB0_GATING_REG */ + SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", + APB0_GATING_REG, 0), + SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", + APB0_GATING_REG, 1), + SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", + APB0_GATING_REG, 2), + SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", + APB0_GATING_REG, 3), + SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", + APB0_GATING_REG, 4), + SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", + APB0_GATING_REG, 5), + SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", + APB0_GATING_REG, 6), + SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", + APB0_GATING_REG, 7), + SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", + APB0_GATING_REG, 8), + SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", + APB0_GATING_REG, 10), + + /* APB1_GATING_REG */ + SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", + APB1_GATING_REG, 0), + SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", + APB1_GATING_REG, 1), + SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", + APB1_GATING_REG, 2), + SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", + APB1_GATING_REG, 3), + SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", + APB1_GATING_REG, 4), + SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", + APB1_GATING_REG, 5), + SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", + APB1_GATING_REG, 6), + SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", + APB1_GATING_REG, 7), + SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", + APB1_GATING_REG, 15), + SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", + APB1_GATING_REG, 16), + SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", + APB1_GATING_REG, 17), + SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", + APB1_GATING_REG, 18), + SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", + APB1_GATING_REG, 19), + SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", + APB1_GATING_REG, 20), + SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", + APB1_GATING_REG, 21), + SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", + APB1_GATING_REG, 22), + SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", + APB1_GATING_REG, 23), + + /* AUDIO_CODEC_SCLK_CFG_REG */ + SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", + AUDIO_CODEC_SCLK_CFG_REG, 31), + + /* USBPHY_CFG_REG */ + SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", + USBPHY_CFG_REG, 6), + SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", + USBPHY_CFG_REG, 7), + SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", + USBPHY_CFG_REG, 8), +}; + +static int +sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) +{ + struct fdt_attach_args * const faa = aux; + + return of_match_compat_data(faa->faa_phandle, compat_data); +} + +static void +sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) +{ + struct sunxi_ccu_softc * const sc = device_private(self); + struct fdt_attach_args * const faa = aux; + enum sun4i_a10_ccu_type type; + + sc->sc_dev = self; + sc->sc_phandle = faa->faa_phandle; + sc->sc_bst = faa->faa_bst; + + sc->sc_resets = sun4i_a10_ccu_resets; + sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); + + sc->sc_clks = sun4i_a10_ccu_clks; + sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); + + if (sunxi_ccu_attach(sc) != 0) + return; + + aprint_naive("\n"); + + type = of_search_compatible(faa->faa_phandle, compat_data)->data; + + switch (type) { + case CCU_A10: + aprint_normal(": A10 CCU\n"); + break; + case CCU_A20: + aprint_normal(": A20 CCU\n"); + break; + } + + sunxi_ccu_print(sc); +} Index: src/sys/arch/arm/sunxi/sun4i_a10_ccu.h diff -u /dev/null src/sys/arch/arm/sunxi/sun4i_a10_ccu.h:1.1 --- /dev/null Fri Oct 6 21:09:21 2017 +++ src/sys/arch/arm/sunxi/sun4i_a10_ccu.h Fri Oct 6 21:09:21 2017 @@ -0,0 +1,221 @@ +/* $NetBSD: sun4i_a10_ccu.h,v 1.1 2017/10/06 21:09:21 jmcneill Exp $ */ + +/*- + * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SUN4I_A10_CCU_H +#define _SUN4I_A10_CCU_H + +#define A10_RST_USB_PHY0 1 +#define A10_RST_USB_PHY1 2 +#define A10_RST_USB_PHY2 3 +#define A10_RST_GPS 4 +#define A10_RST_DE_BE0 5 +#define A10_RST_DE_BE1 6 +#define A10_RST_DE_FE0 7 +#define A10_RST_DE_FE1 8 +#define A10_RST_DE_MP 9 +#define A10_RST_TVE0 10 +#define A10_RST_TCON0 11 +#define A10_RST_TVE1 12 +#define A10_RST_TCON1 13 +#define A10_RST_CSI0 14 +#define A10_RST_CSI1 15 +#define A10_RST_VE 16 +#define A10_RST_ACE 17 +#define A10_RST_LVDS 18 +#define A10_RST_GPU 19 +#define A10_RST_HDMI_H 20 +#define A10_RST_HDMI_SYS 21 +#define A10_RST_HDMI_AUDIO_DM 22 + +#define A10_CLK_HOSC 1 +#define A10_CLK_PLL_CORE 2 +#define A10_CLK_PLL_AUDIO_BASE 3 +#define A10_CLK_PLL_AUDIO 4 +#define A10_CLK_PLL_AUDIO_2X 5 +#define A10_CLK_PLL_AUDIO_4X 6 +#define A10_CLK_PLL_AUDIO_8X 7 +#define A10_CLK_PLL_VIDEO0 8 +#define A10_CLK_PLL_VIDEO0_2X 9 +#define A10_CLK_PLL_VE 10 +#define A10_CLK_PLL_DDR_BASE 11 +#define A10_CLK_PLL_DDR 12 +#define A10_CLK_PLL_DDR_OTHER 13 +#define A10_CLK_PLL_PERIPH_BASE 14 +#define A10_CLK_PLL_PERIPH 15 +#define A10_CLK_PLL_PERIPH_SATA 16 +#define A10_CLK_PLL_VIDEO1 17 +#define A10_CLK_PLL_VIDEO1_2X 18 +#define A10_CLK_PLL_GPU 19 +#define A10_CLK_CPU 20 +#define A10_CLK_AXI 21 +#define A10_CLK_AXI_DRAM 22 +#define A10_CLK_AHB 23 +#define A10_CLK_APB0 24 +#define A10_CLK_APB1 25 +#define A10_CLK_AHB_OTG 26 +#define A10_CLK_AHB_EHCI0 27 +#define A10_CLK_AHB_OHCI0 28 +#define A10_CLK_AHB_EHCI1 29 +#define A10_CLK_AHB_OHCI1 30 +#define A10_CLK_AHB_SS 31 +#define A10_CLK_AHB_DMA 32 +#define A10_CLK_AHB_BIST 33 +#define A10_CLK_AHB_MMC0 34 +#define A10_CLK_AHB_MMC1 35 +#define A10_CLK_AHB_MMC2 36 +#define A10_CLK_AHB_MMC3 37 +#define A10_CLK_AHB_MS 38 +#define A10_CLK_AHB_NAND 39 +#define A10_CLK_AHB_SDRAM 40 +#define A10_CLK_AHB_ACE 41 +#define A10_CLK_AHB_EMAC 42 +#define A10_CLK_AHB_TS 43 +#define A10_CLK_AHB_SPI0 44 +#define A10_CLK_AHB_SPI1 45 +#define A10_CLK_AHB_SPI2 46 +#define A10_CLK_AHB_SPI3 47 +#define A10_CLK_AHB_PATA 48 +#define A10_CLK_AHB_SATA 49 +#define A10_CLK_AHB_GPS 50 +#define A10_CLK_AHB_HSTIMER 51 +#define A10_CLK_AHB_VE 52 +#define A10_CLK_AHB_TVD 53 +#define A10_CLK_AHB_TVE0 54 +#define A10_CLK_AHB_TVE1 55 +#define A10_CLK_AHB_LCD0 56 +#define A10_CLK_AHB_LCD1 57 +#define A10_CLK_AHB_CSI0 58 +#define A10_CLK_AHB_CSI1 59 +#define A10_CLK_AHB_HDMI0 60 +#define A10_CLK_AHB_HDMI1 61 +#define A10_CLK_AHB_DE_BE0 62 +#define A10_CLK_AHB_DE_BE1 63 +#define A10_CLK_AHB_DE_FE0 64 +#define A10_CLK_AHB_DE_FE1 65 +#define A10_CLK_AHB_GMAC 66 +#define A10_CLK_AHB_MP 67 +#define A10_CLK_AHB_GPU 68 +#define A10_CLK_APB0_CODEC 69 +#define A10_CLK_APB0_SPDIF 70 +#define A10_CLK_APB0_I2S0 71 +#define A10_CLK_APB0_AC97 72 +#define A10_CLK_APB0_I2S1 73 +#define A10_CLK_APB0_PIO 74 +#define A10_CLK_APB0_IR0 75 +#define A10_CLK_APB0_IR1 76 +#define A10_CLK_APB0_I2S2 77 +#define A10_CLK_APB0_KEYPAD 78 +#define A10_CLK_APB1_I2C0 79 +#define A10_CLK_APB1_I2C1 80 +#define A10_CLK_APB1_I2C2 81 +#define A10_CLK_APB1_I2C3 82 +#define A10_CLK_APB1_CAN 83 +#define A10_CLK_APB1_SCR 84 +#define A10_CLK_APB1_PS20 85 +#define A10_CLK_APB1_PS21 86 +#define A10_CLK_APB1_I2C4 87 +#define A10_CLK_APB1_UART0 88 +#define A10_CLK_APB1_UART1 89 +#define A10_CLK_APB1_UART2 90 +#define A10_CLK_APB1_UART3 91 +#define A10_CLK_APB1_UART4 92 +#define A10_CLK_APB1_UART5 93 +#define A10_CLK_APB1_UART6 94 +#define A10_CLK_APB1_UART7 95 +#define A10_CLK_NAND 96 +#define A10_CLK_MS 97 +#define A10_CLK_MMC0 98 +#define A10_CLK_MMC0_OUTPUT 99 +#define A10_CLK_MMC0_SAMPLE 100 +#define A10_CLK_MMC1 101 +#define A10_CLK_MMC1_OUTPUT 102 +#define A10_CLK_MMC1_SAMPLE 103 +#define A10_CLK_MMC2 104 +#define A10_CLK_MMC2_OUTPUT 105 +#define A10_CLK_MMC2_SAMPLE 106 +#define A10_CLK_MMC3 107 +#define A10_CLK_MMC3_OUTPUT 108 +#define A10_CLK_MMC3_SAMPLE 109 +#define A10_CLK_TS 110 +#define A10_CLK_SS 111 +#define A10_CLK_SPI0 112 +#define A10_CLK_SPI1 113 +#define A10_CLK_SPI2 114 +#define A10_CLK_PATA 115 +#define A10_CLK_IR0 116 +#define A10_CLK_IR1 117 +#define A10_CLK_I2S0 118 +#define A10_CLK_AC97 119 +#define A10_CLK_SPDIF 120 +#define A10_CLK_KEYPAD 121 +#define A10_CLK_SATA 122 +#define A10_CLK_USB_OHCI0 123 +#define A10_CLK_USB_OHCI1 124 +#define A10_CLK_USB_PHY 125 +#define A10_CLK_GPS 126 +#define A10_CLK_SPI3 127 +#define A10_CLK_I2S1 128 +#define A10_CLK_I2S2 129 +#define A10_CLK_DRAM_VE 130 +#define A10_CLK_DRAM_CSI0 131 +#define A10_CLK_DRAM_CSI1 132 +#define A10_CLK_DRAM_TS 133 +#define A10_CLK_DRAM_TVD 134 +#define A10_CLK_DRAM_TVE0 135 +#define A10_CLK_DRAM_TVE1 136 +#define A10_CLK_DRAM_OUT 137 +#define A10_CLK_DRAM_DE_FE1 138 +#define A10_CLK_DRAM_DE_FE0 139 +#define A10_CLK_DRAM_DE_BE0 140 +#define A10_CLK_DRAM_DE_BE1 141 +#define A10_CLK_DRAM_MP 142 +#define A10_CLK_DRAM_ACE 143 +#define A10_CLK_DE_BE0 144 +#define A10_CLK_DE_BE1 145 +#define A10_CLK_DE_FE0 146 +#define A10_CLK_DE_FE1 147 +#define A10_CLK_DE_MP 148 +#define A10_CLK_TCON0_CH0 149 +#define A10_CLK_TCON1_CH0 150 +#define A10_CLK_CSI_SCLK 151 +#define A10_CLK_TVD_SCLK2 152 +#define A10_CLK_TVD 153 +#define A10_CLK_TCON0_CH1_SCLK2 154 +#define A10_CLK_TCON0_CH1 155 +#define A10_CLK_TCON1_CH1_SCLK2 156 +#define A10_CLK_TCON1_CH1 157 +#define A10_CLK_CSI0 158 +#define A10_CLK_CSI1 159 +#define A10_CLK_CODEC 160 +#define A10_CLK_VE 161 +#define A10_CLK_AVS 162 +#define A10_CLK_ACE 163 +#define A10_CLK_HDMI 164 +#define A10_CLK_GPU 165 + +#endif /* !_SUN4I_A10_CCU_H */ Index: src/sys/arch/arm/sunxi/sun7i_a20_ccu.h diff -u /dev/null src/sys/arch/arm/sunxi/sun7i_a20_ccu.h:1.1 --- /dev/null Fri Oct 6 21:09:21 2017 +++ src/sys/arch/arm/sunxi/sun7i_a20_ccu.h Fri Oct 6 21:09:21 2017 @@ -0,0 +1,40 @@ +/* $NetBSD: sun7i_a20_ccu.h,v 1.1 2017/10/06 21:09:21 jmcneill Exp $ */ + +/*- + * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SUN7I_A20_CCU_H +#define _SUN7I_A20_CCU_H + +#include <arm/sunxi/sun4i_a10_ccu.h> + +#define A20_CLK_MBUS 166 +#define A20_CLK_HDMI1_SLOW 167 +#define A20_CLK_HDMI1 168 +#define A20_CLK_OUT_A 169 +#define A20_CLK_OUT_B 170 + +#endif /* !_SUN7I_A20_CCU_H */