Module Name: src
Committed By: msaitoh
Date: Mon Jan 15 06:08:41 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
To generate a diff of this commit:
cvs rdiff -u -r1.108 -r1.109 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.108 src/sys/arch/x86/include/specialreg.h:1.109
--- src/sys/arch/x86/include/specialreg.h:1.108 Sat Jan 13 17:55:57 2018
+++ src/sys/arch/x86/include/specialreg.h Mon Jan 15 06:08:40 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.108 2018/01/13 17:55:57 jdolecek Exp $ */
+/* $NetBSD: specialreg.h,v 1.109 2018/01/15 06:08:40 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -322,6 +322,7 @@
* %eax: The Maximum input value for supported subleaf.
* %ebx: Feature bits.
* %ecx: Feature bits.
+ * %edx: Feature bits.
*/
/* %ebx */
@@ -396,10 +397,12 @@
#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
+#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
- "\33" "IBRS" "\34" "STIBP"
+ "\33" "IBRS" "\34" "STIBP" \
+ "\36" "ARCH_CAP"
/*
* CPUID Processor extended state Enumeration Fn0000000d
