Module Name: src
Committed By: skrll
Date: Sun Aug 5 07:49:02 UTC 2018
Modified Files:
src/sys/arch/aarch64/include: armreg.h
Log Message:
More whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.13 src/sys/arch/aarch64/include/armreg.h:1.14
--- src/sys/arch/aarch64/include/armreg.h:1.13 Wed Aug 1 13:42:58 2018
+++ src/sys/arch/aarch64/include/armreg.h Sun Aug 5 07:49:02 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.13 2018/08/01 13:42:58 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.14 2018/08/05 07:49:02 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -80,12 +80,12 @@ AARCH64REG_READ_INLINE(ctr_el0) // Cach
#define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag
#define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2)
-AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
+AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
#define DCZID_DZP __BIT(4) // Data Zero Prohibited
#define DCZID_BS __BITS(3,0) // Block Size (log2 - 2)
-AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
+AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
AARCH64REG_WRITE_INLINE(fpcr)
#define FPCR_AHP __BIT(26) // Alternative Half Precision
@@ -144,7 +144,7 @@ AARCH64REG_READ_INLINE(tpidrro_el0) // T
*/
AARCH64REG_READ_INLINE(aidr_el1)
-AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
+AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
#define CBAR_PA __BITS(47,18)
@@ -261,75 +261,75 @@ AARCH64REG_READ_INLINE(mpidr_el1)
AARCH64REG_READ_INLINE(mvfr0_el1)
-#define MVFR0_FPROUND __BITS(31,28)
-#define MVFR0_FPROUND_NEAREST 0
+#define MVFR0_FPROUND __BITS(31,28)
+#define MVFR0_FPROUND_NEAREST 0
#define MVFR0_FPROUND_ALL 1
-#define MVFR0_FPSHVEC __BITS(27,24)
+#define MVFR0_FPSHVEC __BITS(27,24)
#define MVFR0_FPSHVEC_NONE 0
-#define MVFR0_FPSHVEC_SHVEC 1
-#define MVFR0_FPSQRT __BITS(23,20)
+#define MVFR0_FPSHVEC_SHVEC 1
+#define MVFR0_FPSQRT __BITS(23,20)
#define MVFR0_FPSQRT_NONE 0
#define MVFR0_FPSQRT_VSQRT 1
-#define MVFR0_FPDIVIDE __BITS(19,16)
-#define MVFR0_FPDIVIDE_NONE 0
-#define MVFR0_FPDIVIDE_VDIV 1
-#define MVFR0_FPTRAP __BITS(15,12)
+#define MVFR0_FPDIVIDE __BITS(19,16)
+#define MVFR0_FPDIVIDE_NONE 0
+#define MVFR0_FPDIVIDE_VDIV 1
+#define MVFR0_FPTRAP __BITS(15,12)
#define MVFR0_FPTRAP_NONE 0
#define MVFR0_FPTRAP_TRAP 1
-#define MVFR0_FPDP __BITS(11,8)
+#define MVFR0_FPDP __BITS(11,8)
#define MVFR0_FPDP_NONE 0
#define MVFR0_FPDP_VFPV2 1
#define MVFR0_FPDP_VFPV3 2
-#define MVFR0_FPSP __BITS(7,4)
+#define MVFR0_FPSP __BITS(7,4)
#define MVFR0_FPSP_NONE 0
#define MVFR0_FPSP_VFPV2 1
#define MVFR0_FPSP_VFPV3 2
-#define MVFR0_SIMDREG __BITS(3,0)
+#define MVFR0_SIMDREG __BITS(3,0)
#define MVFR0_SIMDREG_NONE 0
-#define MVFR0_SIMDREG_16x64 1
-#define MVFR0_SIMDREG_32x64 2
+#define MVFR0_SIMDREG_16x64 1
+#define MVFR0_SIMDREG_32x64 2
AARCH64REG_READ_INLINE(mvfr1_el1)
-#define MVFR1_SIMDFMAC __BITS(31,28)
-#define MVFR1_SIMDFMAC_NONE 0
-#define MVFR1_SIMDFMAC_FMAC 1
-#define MVFR1_FPHP __BITS(27,24)
+#define MVFR1_SIMDFMAC __BITS(31,28)
+#define MVFR1_SIMDFMAC_NONE 0
+#define MVFR1_SIMDFMAC_FMAC 1
+#define MVFR1_FPHP __BITS(27,24)
#define MVFR1_FPHP_NONE 0
-#define MVFR1_FPHP_HALF_SINGLE 1
-#define MVFR1_FPHP_HALF_DOUBLE 2
-#define MVFR1_SIMDHP __BITS(23,20)
+#define MVFR1_FPHP_HALF_SINGLE 1
+#define MVFR1_FPHP_HALF_DOUBLE 2
+#define MVFR1_SIMDHP __BITS(23,20)
#define MVFR1_SIMDHP_NONE 0
#define MVFR1_SIMDHP_HALF 1
-#define MVFR1_SIMDSP __BITS(19,16)
+#define MVFR1_SIMDSP __BITS(19,16)
#define MVFR1_SIMDSP_NONE 0
-#define MVFR1_SIMDSP_SINGLE 1
-#define MVFR1_SIMDINT __BITS(15,12)
+#define MVFR1_SIMDSP_SINGLE 1
+#define MVFR1_SIMDINT __BITS(15,12)
#define MVFR1_SIMDINT_NONE 0
-#define MVFR1_SIMDINT_INTEGER 1
-#define MVFR1_SIMDLS __BITS(11,8)
+#define MVFR1_SIMDINT_INTEGER 1
+#define MVFR1_SIMDLS __BITS(11,8)
#define MVFR1_SIMDLS_NONE 0
-#define MVFR1_SIMDLS_LOADSTORE 1
-#define MVFR1_FPDNAN __BITS(7,4)
+#define MVFR1_SIMDLS_LOADSTORE 1
+#define MVFR1_FPDNAN __BITS(7,4)
#define MVFR1_FPDNAN_NONE 0
#define MVFR1_FPDNAN_NAN 1
-#define MVFR1_FPFTZ __BITS(3,0)
+#define MVFR1_FPFTZ __BITS(3,0)
#define MVFR1_FPFTZ_NONE 0
-#define MVFR1_FPFTZ_DENORMAL 1
+#define MVFR1_FPFTZ_DENORMAL 1
AARCH64REG_READ_INLINE(mvfr2_el1)
-#define MVFR2_FPMISC __BITS(7,4)
+#define MVFR2_FPMISC __BITS(7,4)
#define MVFR2_FPMISC_NONE 0
#define MVFR2_FPMISC_SEL 1
-#define MVFR2_FPMISC_DROUND 2
-#define MVFR2_FPMISC_ROUNDINT 3
-#define MVFR2_FPMISC_MAXMIN 4
-#define MVFR2_SIMDMISC __BITS(3,0)
-#define MVFR2_SIMDMISC_NONE 0
-#define MVFR2_SIMDMISC_DROUND 1
+#define MVFR2_FPMISC_DROUND 2
+#define MVFR2_FPMISC_ROUNDINT 3
+#define MVFR2_FPMISC_MAXMIN 4
+#define MVFR2_SIMDMISC __BITS(3,0)
+#define MVFR2_SIMDMISC_NONE 0
+#define MVFR2_SIMDMISC_DROUND 1
#define MVFR2_SIMDMISC_ROUNDINT 2
-#define MVFR2_SIMDMISC_MAXMIN 3
+#define MVFR2_SIMDMISC_MAXMIN 3
AARCH64REG_READ_INLINE(revidr_el1)
@@ -339,29 +339,29 @@ AARCH64REG_READ_INLINE(revidr_el1)
AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
AARCH64REG_WRITE_INLINE(cpacr_el1)
-#define CPACR_TTA __BIT(28) // System Register Access Traps
-#define CPACR_FPEN __BITS(21,20)
-#define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
-#define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
-#define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
-#define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
+#define CPACR_TTA __BIT(28) // System Register Access Traps
+#define CPACR_FPEN __BITS(21,20)
+#define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
+#define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
+#define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
+#define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register
AARCH64REG_WRITE_INLINE(csselr_el1)
-#define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
-#define CSSELR_IND __BIT(0) // Instruction not Data bit
+#define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
+#define CSSELR_IND __BIT(0) // Instruction not Data bit
AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register
AARCH64REG_WRITE_INLINE(daif)
AARCH64REG_WRITEIMM_INLINE(daifclr)
AARCH64REG_WRITEIMM_INLINE(daifset)
-#define DAIF_D __BIT(9) // Debug Exception Mask
-#define DAIF_A __BIT(8) // SError Abort Mask
-#define DAIF_I __BIT(7) // IRQ Mask
-#define DAIF_F __BIT(6) // FIQ Mask
-#define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
+#define DAIF_D __BIT(9) // Debug Exception Mask
+#define DAIF_A __BIT(8) // SError Abort Mask
+#define DAIF_I __BIT(7) // IRQ Mask
+#define DAIF_F __BIT(6) // FIQ Mask
+#define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register
AARCH64REG_WRITE_INLINE(elr_el1)
@@ -369,44 +369,44 @@ AARCH64REG_WRITE_INLINE(elr_el1)
AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register
AARCH64REG_WRITE_INLINE(esr_el1)
-#define ESR_EC __BITS(31,26) // Exception Cause
-#define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
-#define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
-#define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
-#define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
-#define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
-#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
-#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
-#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
-#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
-#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
-#define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
-#define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
-#define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
-#define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
-#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
-#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
-#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
-#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
-#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
-#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
-#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
-#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
-#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
-#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
-#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
-#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
-#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
-#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
-#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
-#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
-#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
-#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
-#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
-#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
-#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
-#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
-#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
+#define ESR_EC __BITS(31,26) // Exception Cause
+#define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
+#define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
+#define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
+#define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
+#define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
+#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
+#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
+#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
+#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
+#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
+#define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
+#define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
+#define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
+#define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
+#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
+#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
+#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
+#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
+#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
+#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
+#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
+#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
+#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
+#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
+#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
+#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
+#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
+#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
+#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
+#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
+#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
+#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
+#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
+#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
+#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
+#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
+#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
#define ESR_ISS_CV __BIT(24) // common
#define ESR_ISS_COND __BITS(23,20) // common
#define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
@@ -438,38 +438,38 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01]
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03
-#define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04
-#define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05
-#define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06
-#define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07
-#define ESR_ISS_FSC_ACCESS_FAULT_0 0x08
-#define ESR_ISS_FSC_ACCESS_FAULT_1 0x09
-#define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a
-#define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b
-#define ESR_ISS_FSC_PERM_FAULT_0 0x0c
-#define ESR_ISS_FSC_PERM_FAULT_1 0x0d
-#define ESR_ISS_FSC_PERM_FAULT_2 0x0e
-#define ESR_ISS_FSC_PERM_FAULT_3 0x0f
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f
-#define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21
-#define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30
-#define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34
-#define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35
-#define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d
-#define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e
+#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00
+#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01
+#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02
+#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03
+#define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04
+#define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05
+#define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06
+#define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07
+#define ESR_ISS_FSC_ACCESS_FAULT_0 0x08
+#define ESR_ISS_FSC_ACCESS_FAULT_1 0x09
+#define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a
+#define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b
+#define ESR_ISS_FSC_PERM_FAULT_0 0x0c
+#define ESR_ISS_FSC_PERM_FAULT_1 0x0d
+#define ESR_ISS_FSC_PERM_FAULT_2 0x0e
+#define ESR_ISS_FSC_PERM_FAULT_3 0x0f
+#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10
+#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14
+#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15
+#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16
+#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17
+#define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18
+#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c
+#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d
+#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e
+#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f
+#define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21
+#define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30
+#define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34
+#define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35
+#define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d
+#define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e
AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
@@ -487,33 +487,33 @@ AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_
AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register
AARCH64REG_WRITE_INLINE(mair_el1)
-#define MAIR_ATTR0 __BITS(7,0)
-#define MAIR_ATTR1 __BITS(15,8)
-#define MAIR_ATTR2 __BITS(23,16)
-#define MAIR_ATTR3 __BITS(31,24)
-#define MAIR_ATTR4 __BITS(39,32)
-#define MAIR_ATTR5 __BITS(47,40)
-#define MAIR_ATTR6 __BITS(55,48)
-#define MAIR_ATTR7 __BITS(63,56)
-#define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck.
-#define MAIR_NORMAL_NC 0x44
-#define MAIR_NORMAL_WT 0xbb
-#define MAIR_NORMAL_WB 0xff
+#define MAIR_ATTR0 __BITS(7,0)
+#define MAIR_ATTR1 __BITS(15,8)
+#define MAIR_ATTR2 __BITS(23,16)
+#define MAIR_ATTR3 __BITS(31,24)
+#define MAIR_ATTR4 __BITS(39,32)
+#define MAIR_ATTR5 __BITS(47,40)
+#define MAIR_ATTR6 __BITS(55,48)
+#define MAIR_ATTR7 __BITS(63,56)
+#define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck.
+#define MAIR_NORMAL_NC 0x44
+#define MAIR_NORMAL_WT 0xbb
+#define MAIR_NORMAL_WB 0xff
AARCH64REG_READ_INLINE(par_el1) // Physical Address Register
AARCH64REG_WRITE_INLINE(par_el1)
-#define PAR_ATTR __BITS(63,56) // F=0 memory attributes
-#define PAR_PA __BITS(47,12) // F=0 physical address
-#define PAR_NS __BIT(9) // F=0 non-secure
-#define PAR_S __BIT(9) // F=1 failure stage
-#define PAR_SHA __BITS(8,7) // F=0 shareability attribute
-#define PAR_SHA_NONE 0
-#define PAR_SHA_OUTER 2
-#define PAR_SHA_INNER 3
-#define PAR_PTW __BIT(8) // F=1 partial table walk
-#define PAR_FST __BITS(6,1) // F=1 fault status code
-#define PAR_F __BIT(0) // translation failed
+#define PAR_ATTR __BITS(63,56) // F=0 memory attributes
+#define PAR_PA __BITS(47,12) // F=0 physical address
+#define PAR_NS __BIT(9) // F=0 non-secure
+#define PAR_S __BIT(9) // F=1 failure stage
+#define PAR_SHA __BITS(8,7) // F=0 shareability attribute
+#define PAR_SHA_NONE 0
+#define PAR_SHA_OUTER 2
+#define PAR_SHA_INNER 3
+#define PAR_PTW __BIT(8) // F=1 partial table walk
+#define PAR_FST __BITS(6,1) // F=1 fault status code
+#define PAR_F __BIT(0) // translation failed
AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register
AARCH64REG_WRITE_INLINE(rmr_el1)
@@ -524,31 +524,31 @@ AARCH64REG_WRITE_INLINE(rvbar_el1)
AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
AARCH64REG_WRITE_INLINE(sctlr_el1)
-#define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
-#define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
-#define SCTLR_M __BIT(0)
-#define SCTLR_A __BIT(1)
-#define SCTLR_C __BIT(2)
-#define SCTLR_SA __BIT(3)
-#define SCTLR_SA0 __BIT(4)
-#define SCTLR_CP15BEN __BIT(5)
-#define SCTLR_THEE __BIT(6)
-#define SCTLR_ITD __BIT(7)
-#define SCTLR_SED __BIT(8)
-#define SCTLR_UMA __BIT(9)
-#define SCTLR_I __BIT(12)
-#define SCTLR_DZE __BIT(14)
-#define SCTLR_UCT __BIT(15)
-#define SCTLR_nTWI __BIT(16)
-#define SCTLR_nTWE __BIT(18)
-#define SCTLR_WXN __BIT(19)
-#define SCTLR_IESB __BIT(21)
-#define SCTLR_SPAN __BIT(23)
-#define SCTLR_EOE __BIT(24)
-#define SCTLR_EE __BIT(25)
-#define SCTLR_UCI __BIT(26)
-#define SCTLR_nTLSMD __BIT(28)
-#define SCTLR_LSMAOE __BIT(29)
+#define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
+#define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
+#define SCTLR_M __BIT(0)
+#define SCTLR_A __BIT(1)
+#define SCTLR_C __BIT(2)
+#define SCTLR_SA __BIT(3)
+#define SCTLR_SA0 __BIT(4)
+#define SCTLR_CP15BEN __BIT(5)
+#define SCTLR_THEE __BIT(6)
+#define SCTLR_ITD __BIT(7)
+#define SCTLR_SED __BIT(8)
+#define SCTLR_UMA __BIT(9)
+#define SCTLR_I __BIT(12)
+#define SCTLR_DZE __BIT(14)
+#define SCTLR_UCT __BIT(15)
+#define SCTLR_nTWI __BIT(16)
+#define SCTLR_nTWE __BIT(18)
+#define SCTLR_WXN __BIT(19)
+#define SCTLR_IESB __BIT(21)
+#define SCTLR_SPAN __BIT(23)
+#define SCTLR_EOE __BIT(24)
+#define SCTLR_EE __BIT(25)
+#define SCTLR_UCI __BIT(26)
+#define SCTLR_nTLSMD __BIT(28)
+#define SCTLR_LSMAOE __BIT(29)
// current EL stack pointer
static __inline uint64_t
@@ -565,50 +565,50 @@ AARCH64REG_WRITE_INLINE(sp_el0)
AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select
AARCH64REG_WRITE_INLINE(spsel)
-#define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels
+#define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels
AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register
AARCH64REG_WRITE_INLINE(spsr_el1)
-#define SPSR_NZCV __BITS(31,28) // mask of N Z C V
-#define SPSR_N __BIT(31) // Negative
-#define SPSR_Z __BIT(30) // Zero
-#define SPSR_C __BIT(29) // Carry
-#define SPSR_V __BIT(28) // oVerflow
-#define SPSR_A32_Q __BIT(27) // A32: Overflow
-#define SPSR_A32_J __BIT(24) // A32: Jazelle Mode
-#define SPSR_A32_IT1 __BIT(23) // A32: IT[1]
-#define SPSR_A32_IT0 __BIT(22) // A32: IT[0]
-#define SPSR_SS __BIT(21) // Software Step
-#define SPSR_IL __BIT(20) // Instruction Length
-#define SPSR_GE __BITS(19,16) // A32: SIMD GE
-#define SPSR_IT7 __BIT(15) // A32: IT[7]
-#define SPSR_IT6 __BIT(14) // A32: IT[6]
-#define SPSR_IT5 __BIT(13) // A32: IT[5]
-#define SPSR_IT4 __BIT(12) // A32: IT[4]
-#define SPSR_IT3 __BIT(11) // A32: IT[3]
-#define SPSR_IT2 __BIT(10) // A32: IT[2]
-#define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask
-#define SPSR_A32_E __BIT(9) // A32: BE Endian Mode
-#define SPSR_A __BIT(8) // Async abort (SError) Mask
-#define SPSR_I __BIT(7) // IRQ Mask
-#define SPSR_F __BIT(6) // FIQ Mask
-#define SPSR_A32_T __BIT(5) // A32 Thumb Mode
-#define SPSR_M __BITS(4,0) // Execution State
-#define SPSR_M_EL3H 0x0d
-#define SPSR_M_EL3T 0x0c
-#define SPSR_M_EL2H 0x09
-#define SPSR_M_EL2T 0x08
-#define SPSR_M_EL1H 0x05
-#define SPSR_M_EL1T 0x04
-#define SPSR_M_EL0T 0x00
-#define SPSR_M_SYS32 0x1f
-#define SPSR_M_UND32 0x1b
-#define SPSR_M_ABT32 0x17
-#define SPSR_M_SVC32 0x13
-#define SPSR_M_IRQ32 0x12
-#define SPSR_M_FIQ32 0x11
-#define SPSR_M_USR32 0x10
+#define SPSR_NZCV __BITS(31,28) // mask of N Z C V
+#define SPSR_N __BIT(31) // Negative
+#define SPSR_Z __BIT(30) // Zero
+#define SPSR_C __BIT(29) // Carry
+#define SPSR_V __BIT(28) // oVerflow
+#define SPSR_A32_Q __BIT(27) // A32: Overflow
+#define SPSR_A32_J __BIT(24) // A32: Jazelle Mode
+#define SPSR_A32_IT1 __BIT(23) // A32: IT[1]
+#define SPSR_A32_IT0 __BIT(22) // A32: IT[0]
+#define SPSR_SS __BIT(21) // Software Step
+#define SPSR_IL __BIT(20) // Instruction Length
+#define SPSR_GE __BITS(19,16) // A32: SIMD GE
+#define SPSR_IT7 __BIT(15) // A32: IT[7]
+#define SPSR_IT6 __BIT(14) // A32: IT[6]
+#define SPSR_IT5 __BIT(13) // A32: IT[5]
+#define SPSR_IT4 __BIT(12) // A32: IT[4]
+#define SPSR_IT3 __BIT(11) // A32: IT[3]
+#define SPSR_IT2 __BIT(10) // A32: IT[2]
+#define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask
+#define SPSR_A32_E __BIT(9) // A32: BE Endian Mode
+#define SPSR_A __BIT(8) // Async abort (SError) Mask
+#define SPSR_I __BIT(7) // IRQ Mask
+#define SPSR_F __BIT(6) // FIQ Mask
+#define SPSR_A32_T __BIT(5) // A32 Thumb Mode
+#define SPSR_M __BITS(4,0) // Execution State
+#define SPSR_M_EL3H 0x0d
+#define SPSR_M_EL3T 0x0c
+#define SPSR_M_EL2H 0x09
+#define SPSR_M_EL2T 0x08
+#define SPSR_M_EL1H 0x05
+#define SPSR_M_EL1T 0x04
+#define SPSR_M_EL0T 0x00
+#define SPSR_M_SYS32 0x1f
+#define SPSR_M_UND32 0x1b
+#define SPSR_M_ABT32 0x17
+#define SPSR_M_SVC32 0x13
+#define SPSR_M_IRQ32 0x12
+#define SPSR_M_FIQ32 0x11
+#define SPSR_M_USR32 0x10
AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
AARCH64REG_WRITE_INLINE(tcr_el1)
@@ -665,13 +665,13 @@ AARCH64REG_WRITE_INLINE(dbgbcr14_el1)
AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15
AARCH64REG_WRITE_INLINE(dbgbcr15_el1)
-#define DBGBCR_BT __BITS(23,20)
-#define DBGBCR_LBN __BITS(19,16)
-#define DBGBCR_SSC __BITS(15,14)
-#define DBGBCR_HMC __BIT(13)
-#define DBGBCR_BAS __BITS(8,5)
-#define DBGBCR_PMC __BITS(2,1)
-#define DBGBCR_E __BIT(0)
+#define DBGBCR_BT __BITS(23,20)
+#define DBGBCR_LBN __BITS(19,16)
+#define DBGBCR_SSC __BITS(15,14)
+#define DBGBCR_HMC __BIT(13)
+#define DBGBCR_BAS __BITS(8,5)
+#define DBGBCR_PMC __BITS(2,1)
+#define DBGBCR_E __BIT(0)
AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0
AARCH64REG_WRITE_INLINE(dbgbvr0_el1)
@@ -739,15 +739,15 @@ AARCH64REG_WRITE_INLINE(dbgwcr14_el1)
AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15
AARCH64REG_WRITE_INLINE(dbgwcr15_el1)
-#define DBGWCR_MASK __BITS(28,24)
-#define DBGWCR_WT __BIT(20)
-#define DBGWCR_LBN __BITS(19,16)
-#define DBGWCR_SSC __BITS(15,14)
-#define DBGWCR_HMC __BIT(13)
-#define DBGWCR_BAS __BITS(12,5)
-#define DBGWCR_LSC __BITS(4,3)
-#define DBGWCR_PAC __BITS(2,1)
-#define DBGWCR_E __BIT(0)
+#define DBGWCR_MASK __BITS(28,24)
+#define DBGWCR_WT __BIT(20)
+#define DBGWCR_LBN __BITS(19,16)
+#define DBGWCR_SSC __BITS(15,14)
+#define DBGWCR_HMC __BIT(13)
+#define DBGWCR_BAS __BITS(12,5)
+#define DBGWCR_LSC __BITS(4,3)
+#define DBGWCR_PAC __BITS(2,1)
+#define DBGWCR_E __BIT(0)
AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0
AARCH64REG_WRITE_INLINE(dbgwvr0_el1)
@@ -782,7 +782,7 @@ AARCH64REG_WRITE_INLINE(dbgwvr14_el1)
AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15
AARCH64REG_WRITE_INLINE(dbgwvr15_el1)
-#define DBGWVR_MASK __BITS(64,3)
+#define DBGWVR_MASK __BITS(64,3)
AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register
@@ -799,12 +799,12 @@ AARCH64REG_READ_INLINE(oslsr_el1) // OS
AARCH64REG_READ_INLINE(pmccfiltr_el0)
AARCH64REG_WRITE_INLINE(pmccfiltr_el0)
-#define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1
-#define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0
-#define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1
-#define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0
-#define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2
-#define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3
+#define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1
+#define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0
+#define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1
+#define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0
+#define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2
+#define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3
AARCH64REG_READ_INLINE(pmccntr_el0)
@@ -817,17 +817,17 @@ AARCH64REG_WRITE_INLINE(pmcntenset_el0)
AARCH64REG_READ_INLINE(pmcr_el0)
AARCH64REG_WRITE_INLINE(pmcr_el0)
-#define PMCR_IMP __BITS(31,24) // Implementor code
-#define PMCR_IDCODE __BITS(23,16) // Identification code
-#define PMCR_N __BITS(15,11) // Number of event counters
-#define PMCR_LC __BIT(6) // Long cycle counter enable
-#define PMCR_DP __BIT(5) // Disable cycle counter when event
- // counting is prohibited
-#define PMCR_X __BIT(4) // Enable export of events
-#define PMCR_D __BIT(3) // Clock divider
-#define PMCR_C __BIT(2) // Cycle counter reset
-#define PMCR_P __BIT(1) // Event counter reset
-#define PMCR_E __BIT(0) // Enable
+#define PMCR_IMP __BITS(31,24) // Implementor code
+#define PMCR_IDCODE __BITS(23,16) // Identification code
+#define PMCR_N __BITS(15,11) // Number of event counters
+#define PMCR_LC __BIT(6) // Long cycle counter enable
+#define PMCR_DP __BIT(5) // Disable cycle counter when event
+ // counting is prohibited
+#define PMCR_X __BIT(4) // Enable export of events
+#define PMCR_D __BIT(3) // Clock divider
+#define PMCR_C __BIT(2) // Cycle counter reset
+#define PMCR_P __BIT(1) // Event counter reset
+#define PMCR_E __BIT(0) // Enable
AARCH64REG_READ_INLINE(pmevcntr1_el0)
@@ -836,15 +836,15 @@ AARCH64REG_WRITE_INLINE(pmevcntr1_el0)
AARCH64REG_READ_INLINE(pmevtyper1_el0)
AARCH64REG_WRITE_INLINE(pmevtyper1_el0)
-#define PMEVTYPER_P __BIT(31) // Don't count events in EL1
-#define PMEVTYPER_U __BIT(30) // Don't count events in EL0
-#define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1
-#define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0
-#define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2
-#define PMEVTYPER_M __BIT(26) // Don't count events in EL3
-#define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same
- // aff1 level
-#define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count
+#define PMEVTYPER_P __BIT(31) // Don't count events in EL1
+#define PMEVTYPER_U __BIT(30) // Don't count events in EL0
+#define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1
+#define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0
+#define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2
+#define PMEVTYPER_M __BIT(26) // Don't count events in EL3
+#define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same
+ // aff1 level
+#define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count
AARCH64REG_WRITE_INLINE(pmintenclr_el1)
AARCH64REG_WRITE_INLINE(pmintenset_el1)
@@ -875,25 +875,25 @@ AARCH64REG_READ_INLINE(cntfrq_el0)
AARCH64REG_READ_INLINE(cnthctl_el2)
AARCH64REG_WRITE_INLINE(cnthctl_el2)
-#define CNTHCTL_EVNTDIR __BIT(3)
-#define CNTHCTL_EVNTEN __BIT(2)
-#define CNTHCTL_EL1PCEN __BIT(1)
-#define CNTHCTL_EL1PCTEN __BIT(0)
+#define CNTHCTL_EVNTDIR __BIT(3)
+#define CNTHCTL_EVNTEN __BIT(2)
+#define CNTHCTL_EL1PCEN __BIT(1)
+#define CNTHCTL_EL1PCTEN __BIT(0)
AARCH64REG_READ_INLINE(cntkctl_el1)
AARCH64REG_WRITE_INLINE(cntkctl_el1)
-#define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL
-#define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN
-#define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL
-#define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN
-#define CNTKCTL_ELNTI __BITS(7,4)
-#define CNTKCTL_EVNTDIR __BIT(3)
-#define CNTKCTL_EVNTEN __BIT(2)
-#define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ
-#define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN
-#define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ
-#define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN
+#define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL
+#define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN
+#define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL
+#define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN
+#define CNTKCTL_ELNTI __BITS(7,4)
+#define CNTKCTL_EVNTDIR __BIT(3)
+#define CNTKCTL_EVNTEN __BIT(2)
+#define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ
+#define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN
+#define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ
+#define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN
AARCH64REG_READ_INLINE(cntp_ctl_el0)
AARCH64REG_WRITE_INLINE(cntp_ctl_el0)
@@ -920,36 +920,36 @@ AARCH64REG_WRITE_INLINE(cntv_tval_el0)
AARCH64REG_READ_INLINE(cntvct_el0)
AARCH64REG_WRITE_INLINE(cntvct_el0)
-#define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted
-#define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
-#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
+#define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted
+#define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
+#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
// ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
#define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF
#define ID_AA64PFR0_EL1_GIC_SHIFT 24
-#define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1
-#define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0
+#define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1
+#define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0
#define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD
-#define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0
-#define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf
+#define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0
+#define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf
#define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP
-#define ID_AA64PFR0_EL1_FP_IMPL 0x0
-#define ID_AA64PFR0_EL1_FP_NONE 0xf
+#define ID_AA64PFR0_EL1_FP_IMPL 0x0
+#define ID_AA64PFR0_EL1_FP_NONE 0xf
#define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling
-#define ID_AA64PFR0_EL1_EL3_NONE 0
-#define ID_AA64PFR0_EL1_EL3_64 1
-#define ID_AA64PFR0_EL1_EL3_64_32 2
+#define ID_AA64PFR0_EL1_EL3_NONE 0
+#define ID_AA64PFR0_EL1_EL3_64 1
+#define ID_AA64PFR0_EL1_EL3_64_32 2
#define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling
-#define ID_AA64PFR0_EL1_EL2_NONE 0
-#define ID_AA64PFR0_EL1_EL2_64 1
-#define ID_AA64PFR0_EL1_EL2_64_32 2
+#define ID_AA64PFR0_EL1_EL2_NONE 0
+#define ID_AA64PFR0_EL1_EL2_64 1
+#define ID_AA64PFR0_EL1_EL2_64_32 2
#define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling
-#define ID_AA64PFR0_EL1_EL1_64 1
-#define ID_AA64PFR0_EL1_EL1_64_32 2
+#define ID_AA64PFR0_EL1_EL1_64 1
+#define ID_AA64PFR0_EL1_EL1_64_32 2
#define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling
-#define ID_AA64PFR0_EL1_EL0_64 1
-#define ID_AA64PFR0_EL1_EL0_64_32 2
+#define ID_AA64PFR0_EL1_EL0_64 1
+#define ID_AA64PFR0_EL1_EL0_64_32 2
// ICC_SRE_EL1: Interrupt Controller System Register Enable register
#define ICC_SRE_EL1_SRE __BIT(0)
