CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2012/09/29 13:02:27
Modified files:
sys/arch/mips64/include: asm.h cpustate.h
sys/arch/mips64/mips64: cache_r5k.c context.S cp0access.S
exception.S lcore_access.S lcore_ddb.S
lcore_float.S tlbhandler.S
sys/arch/sgi/sgi: ip30_nmi.S locore.S
Log message:
Introduce assembly macros for specific processor hazards: tlb update, status
register update, status register update causing a change to the interrupt
enable flag, and a few other arcane ones. <mips64/asm.h> will provide
(supposedly sane) defaults, and <machine/asm.h> may override these with
better tuned versions.
Use these macros instead of random strings of nop in the various .S files
requiring hazard workarounds.
