CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2012/09/29 15:37:03
Modified files:
sys/arch/mips64/conf: files.mips64
sys/arch/mips64/include: asm.h cache.h cpu.h mips_opcode.h pte.h
sys/arch/mips64/mips64: context.S cp0access.S cpu.c db_disasm.c
db_machdep.c lcore_access.S
mips64_machdep.c pmap.c tlbhandler.S
trap.c vm_machdep.c
Added files:
sys/arch/mips64/mips64: cache_tfp.c cache_tfp_subr.S
exception_tfp.S tlb_tfp.S
Log message:
Basic R8000 processor support. R8000 processors require MMU-specific code,
exception-specific code, clock-specific code, and L1 cache-specific code. L2
cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI
Power Challenge (IP21) and are not covered by this commit.
R8000 processors also are 64-bit only processors with 64-bit coprocessor 0
registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit
code to run with sign-extended addresses and registers.
The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However,
trap() is split into a high-level wrapper and a new function, itsa(),
responsible for the actual trap servicing (which name couldn't be helped
because I'm an incorrigible punster). While an R8000 exception may cause
(via trap() ) multiple exceptions to be serviced, non-R8000 processors will
always service one exception in trap(), but they are nevertheless affected
by this code split.
