CVSROOT: /cvs Module name: src Changes by: m...@cvs.openbsd.org 2012/09/29 13:24:31
Modified files: sys/arch/loongson/dev: bonito.c glx.c sys/arch/loongson/loongson: isa_machdep.c sys/arch/mips64/include: cpu.h trap.h sys/arch/mips64/mips64: cache_r4k.c cache_r5k.c cpu.c fp_emulate.c softintr.c trap.c sys/arch/octeon/dev: octeon_intr.c sys/arch/octeon/octeon: lock_machdep.c sys/arch/sgi/hpc: hpc.c sys/arch/sgi/localbus: int.c sys/arch/sgi/sgi: intr_template.c lock_machdep.c machdep.c Log message: Handle the coprocessor 0 cause and status registers as a 64 bit value now, as some odd mips designs need moro than 32 bits in there. This causes a lot of mechanical changes everywhere getsr() is used.