Dear Trent Piepho, > There are two bits which control the CS line in the CTRL0 register: > LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS > in SPI mode. > > LOCK_CS keeps CS asserted though the entire transfer. This should > always be set. The DMA code will always set it, explicitly on the > first segment of the first transfer, and then implicitly on all the > rest by never clearing the bit from the value read from the ctrl0 > register. > > The PIO code will explicitly set it for the first transfer, leave it > set for intermediate transfers, and then clear it for the final > transfer. It should not clear it. > > The only reason to not set LOCK_CS would be to attempt an altered > protocol where CS pulses between each word. Though don't get your > hopes up if you want to do this, as the hardware doesn't appear to do > this in any sane manner. It appears to be related to the hardware > FIFO fill level. > > The code can be simplified by just setting LOCK_CS once and then not > needing to deal with it at all in the PIO and DMA transfer functions. > > Signed-off-by: Trent Piepho <tpie...@gmail.com> > Cc: Marek Vasut <ma...@denx.de> > Cc: Fabio Estevam <fabio.este...@freescale.com> > Cc: Shawn Guo <shawn....@linaro.org> [...]
This is not V1 of patches, but changelog is missing. Otherwise, I'm out of the office, so I'll review and test on monday earliest. Best regards, Marek Vasut ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
