Dear Mark Brown, > On Tue, Oct 01, 2013 at 01:14:25PM -0700, Trent Piepho wrote: > > There are two bits which control the CS line in the CTRL0 register: > > LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS > > in SPI mode. > > Applied all, thanks.
Did the patches undergo any kind of testing? I was busy so I couldn't even review them yet, sorry. Best regards, Marek Vasut ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60135031&iu=/4140/ostg.clktrk _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
