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On Thu, 12 Jul 2001 16:19:06 -0700, Mcgrath, Jim wrote:
>A minor correction of one part of Hale's response:
>[...]
>This is correct for Multiword DMA, but not for Ultra DMA. The host can
>never just deassert DMACK- and do an IO cycle with the drive having DMARQ
>still asserted. Instead, it has to legally terminate the DMA burst by the
>following sequence:
>[...]
Yes, Jim is correct. But of course the device can reassert DMARQ
nearly immediately, even before the host's IOR-/IOW- cycle is
completed.
>PS technically table 10 should be updated - it says that the register access
>rules do not apply to Ultra DMA when DMACK- is asserted (i.e. during a DMA
>burst). There is a lot of sections that say you cannot do a PIO while
>DMACK- is asserted (for instance, all of the register descriptions), but
>since table 10 is covering every case but this one it seems a shame not to
>cover this as well (maybe this is done in ATA 6?).
The problem is that while a Ultra DMA burst is active there is no
IOR- or IOW- signal on the interface. I never could figure out a
clean way to describe that in the IOR-/IOW- tables so I excluded the
time frame of an Ultra DMA data burst by saying the tables did not
apply. Perhaps different wording could be found to describe this
condition?
*** Hale Landis *** [EMAIL PROTECTED] ***
*** Niwot, CO USA *** www.ata-atapi.com ***
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