On Sun, Oct 08, 2023 at 07:42:54PM +0200, Mark Kettenis wrote:
> Hector Martin has added support for the BCM4388 that is found on the
> last generation of Apple Macs. Based on his commits I've managed to
> get it working on my M2 Pro mini. I still have to clean up some of
> that stuff, but here is a forst batch of two diffs.
>
> The changes to dev/ic/bwfm.c correspond to:
>
> https://github.com/AsahiLinux/linux/commit/81e3cc7bec8b9d9c436f63662d8fcfda4f637807
>
> The changes to dev/pci/if_bwfm_pci.c corrspond to:
>
> https://github.com/AsahiLinux/linux/commit/8190add8671fc49c12d04b5ac8fced70f835e69f
>
> Both changes seem to be a good idea and potentially affect other chips
> as well. So if you have a machine with bwfm(4), please test.
>
> ok?
>
This bwfm on my Rpi4 seems to work, can still scan, associate, and pass
packets.
bwfm0 at sdmmc0 function 1
Not sure I grok this enough to give an ok though.
-ml
>
> Index: dev/ic/bwfm.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/ic/bwfm.c,v
> retrieving revision 1.109
> diff -u -p -r1.109 bwfm.c
> --- dev/ic/bwfm.c 28 Mar 2023 14:01:42 -0000 1.109
> +++ dev/ic/bwfm.c 8 Oct 2023 17:29:35 -0000
> @@ -1089,15 +1089,9 @@ void
> bwfm_chip_ai_reset(struct bwfm_softc *sc, struct bwfm_core *core,
> uint32_t prereset, uint32_t reset, uint32_t postreset)
> {
> - struct bwfm_core *core2 = NULL;
> int i;
>
> - if (core->co_id == BWFM_AGENT_CORE_80211)
> - core2 = bwfm_chip_get_core_idx(sc, BWFM_AGENT_CORE_80211, 1);
> -
> bwfm_chip_ai_disable(sc, core, prereset, reset);
> - if (core2)
> - bwfm_chip_ai_disable(sc, core2, prereset, reset);
>
> for (i = 50; i > 0; i--) {
> if ((sc->sc_buscore_ops->bc_read(sc,
> @@ -1110,32 +1104,12 @@ bwfm_chip_ai_reset(struct bwfm_softc *sc
> }
> if (i == 0)
> printf("%s: timeout on core reset\n", DEVNAME(sc));
> - if (core2) {
> - for (i = 50; i > 0; i--) {
> - if ((sc->sc_buscore_ops->bc_read(sc,
> - core2->co_wrapbase + BWFM_AGENT_RESET_CTL) &
> - BWFM_AGENT_RESET_CTL_RESET) == 0)
> - break;
> - sc->sc_buscore_ops->bc_write(sc,
> - core2->co_wrapbase + BWFM_AGENT_RESET_CTL, 0);
> - delay(60);
> - }
> - if (i == 0)
> - printf("%s: timeout on core reset\n", DEVNAME(sc));
> - }
>
> sc->sc_buscore_ops->bc_write(sc,
> core->co_wrapbase + BWFM_AGENT_IOCTL,
> postreset | BWFM_AGENT_IOCTL_CLK);
> sc->sc_buscore_ops->bc_read(sc,
> core->co_wrapbase + BWFM_AGENT_IOCTL);
> - if (core2) {
> - sc->sc_buscore_ops->bc_write(sc,
> - core2->co_wrapbase + BWFM_AGENT_IOCTL,
> - postreset | BWFM_AGENT_IOCTL_CLK);
> - sc->sc_buscore_ops->bc_read(sc,
> - core2->co_wrapbase + BWFM_AGENT_IOCTL);
> - }
> }
>
> void
> @@ -1338,6 +1312,7 @@ bwfm_chip_ca7_set_passive(struct bwfm_so
> {
> struct bwfm_core *core;
> uint32_t val;
> + int i = 0;
>
> core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7);
> val = sc->sc_buscore_ops->bc_read(sc,
> @@ -1347,10 +1322,11 @@ bwfm_chip_ca7_set_passive(struct bwfm_so
> BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
> BWFM_AGENT_IOCTL_ARMCR4_CPUHALT);
>
> - core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_80211);
> - sc->sc_chip.ch_core_reset(sc, core, BWFM_AGENT_D11_IOCTL_PHYRESET |
> - BWFM_AGENT_D11_IOCTL_PHYCLOCKEN, BWFM_AGENT_D11_IOCTL_PHYCLOCKEN,
> - BWFM_AGENT_D11_IOCTL_PHYCLOCKEN);
> + while ((core = bwfm_chip_get_core_idx(sc, BWFM_AGENT_CORE_80211, i++)))
> + sc->sc_chip.ch_core_disable(sc, core,
> + BWFM_AGENT_D11_IOCTL_PHYRESET |
> + BWFM_AGENT_D11_IOCTL_PHYCLOCKEN,
> + BWFM_AGENT_D11_IOCTL_PHYCLOCKEN);
> }
>
> int
> Index: dev/pci/if_bwfm_pci.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/if_bwfm_pci.c,v
> retrieving revision 1.75
> diff -u -p -r1.75 if_bwfm_pci.c
> --- dev/pci/if_bwfm_pci.c 30 Dec 2022 14:10:17 -0000 1.75
> +++ dev/pci/if_bwfm_pci.c 8 Oct 2023 17:29:35 -0000
> @@ -134,6 +134,10 @@ struct bwfm_pci_softc {
> bus_space_handle_t sc_reg_ioh;
> bus_size_t sc_reg_ios;
>
> + bus_space_tag_t sc_pcie_iot;
> + bus_space_handle_t sc_pcie_ioh;
> + bus_size_t sc_pcie_ios;
> +
> bus_space_tag_t sc_tcm_iot;
> bus_space_handle_t sc_tcm_ioh;
> bus_size_t sc_tcm_ios;
> @@ -379,6 +383,10 @@ bwfm_pci_attach(struct device *parent, s
> goto bar1;
> }
>
> + sc->sc_pcie_iot = sc->sc_reg_iot;
> + bus_space_subregion(sc->sc_reg_iot, sc->sc_reg_ioh, 0x2000,
> + sc->sc_reg_ios - 0x2000, &sc->sc_pcie_ioh);
> +
> sc->sc_pc = pa->pa_pc;
> sc->sc_tag = pa->pa_tag;
> sc->sc_id = pa->pa_id;
> @@ -458,11 +466,11 @@ bwfm_pci_preinit(struct bwfm_softc *bwfm
> #endif
>
> bwfm_pci_select_core(sc, BWFM_AGENT_CORE_PCIE2);
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_CONFIGADDR, 0x4e0);
> - reg = bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + reg = bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_CONFIGDATA);
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_CONFIGDATA, reg);
>
> switch (bwfm->sc_chip.ch_chip) {
> @@ -1438,10 +1446,10 @@ bwfm_pci_ring_bell(struct bwfm_pci_softc
> struct bwfm_pci_msgring *ring)
> {
> if (sc->sc_shared_flags & BWFM_SHARED_INFO_SHARED_DAR)
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_0, 1);
> else
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_H2D_MAILBOX_0, 1);
> }
>
> @@ -1889,13 +1897,13 @@ bwfm_pci_buscore_reset(struct bwfm_softc
> };
>
> for (i = 0; i < nitems(cfg_offset); i++) {
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_CONFIGADDR, cfg_offset[i]);
> - reg = bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + reg = bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_CONFIGDATA);
> DPRINTFN(3, ("%s: config offset 0x%04x, value 0x%04x\n",
> DEVNAME(sc), cfg_offset[i], reg));
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_CONFIGDATA, reg);
> }
> }
> @@ -2389,11 +2397,11 @@ void
> bwfm_pci_intr_enable(struct bwfm_pci_softc *sc)
> {
> if (sc->sc_pcireg64)
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_MAILBOXMASK,
> BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H_DB);
> else
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_MAILBOXMASK,
> BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_0 |
> BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_1 |
> @@ -2404,10 +2412,10 @@ void
> bwfm_pci_intr_disable(struct bwfm_pci_softc *sc)
> {
> if (sc->sc_pcireg64)
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_MAILBOXMASK, 0);
> else
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_MAILBOXMASK, 0);
> }
>
> @@ -2415,10 +2423,10 @@ uint32_t
> bwfm_pci_intr_status(struct bwfm_pci_softc *sc)
> {
> if (sc->sc_pcireg64)
> - return bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + return bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_MAILBOXINT);
> else
> - return bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + return bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_MAILBOXINT);
> }
>
> @@ -2426,10 +2434,10 @@ void
> bwfm_pci_intr_ack(struct bwfm_pci_softc *sc, uint32_t status)
> {
> if (sc->sc_pcireg64)
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_MAILBOXINT, status);
> else
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_MAILBOXINT, status);
> }
>
> @@ -2437,10 +2445,10 @@ uint32_t
> bwfm_pci_intmask(struct bwfm_pci_softc *sc)
> {
> if (sc->sc_pcireg64)
> - return bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + return bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_INTMASK);
> else
> - return bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + return bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_INTMASK);
> }
>
> @@ -2451,10 +2459,10 @@ bwfm_pci_hostready(struct bwfm_pci_softc
> return;
>
> if (sc->sc_shared_flags & BWFM_SHARED_INFO_SHARED_DAR)
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_1, 1);
> else
> - bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh,
> + bus_space_write_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
> BWFM_PCI_PCIE2REG_H2D_MAILBOX_1, 1);
> }
>
>
