Luis Cupido wrote:
That is not by any means a CPLD. it is a big FPGA and I bet it would be doing a bazilon things besides the divider.
It shares the CPLD's problems of ground and VCC bounce. The Virtex was completely empty otherwise and the counter was stoppable, so it was easy to see the culprit.
Having a hundred ground pins should be more of an advantage and wether the innards are fine-grained (FPGA) or sum-of-products-cells (CPLD) really does not matter. 73s, Gerhard, DK4XP _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
