Fabio Eboli wrote:
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
The simulation indicates that the TAC capacitor charging current is far
from constant whilst charging.
This is due to the use of saturated switches rather than current
steering switches.
The capacitor charging current is poorly controlled.
So in this respect your circuit fails miserably.
bruce
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