On 12/28/12 9:34 AM, Chris Albertson wrote:
On Thu, Dec 27, 2012 at 1:36 AM, Hal Murray <hmur...@megapathdsl.net> wrote:
One idea that I like is to first get a large FPGA. Then you load in a
"soft CPU" and then you run an OS and NTP on the soft CPU. Inside
the softCPU the counter is implemented like it is in a real CPU but
you can add the ability for a PPS to "latch" it. Basicaly you move
the interrupt handler to hardware. The trick is if you can get
good enough performance out of the soft CPU? There is some
intelectual property problems with some soft CPS but I'm pretty sure
there are free SPARC CPS you can use and SPARC is ideal for this as it
can run BSD Unix.
The LEON core for the SPARC V8 is free and available from gaisler.com.
The free version doesn't come with testbenches or support, but all the
source and documentation is there. There's a fairly active mailing list
for support with participation by the guys who implemented the core.
It's a fairly easy "drop in" to either Xilinx or Actel FPGAs, and it's
configurable (e.g. if you don't want floating point you don't compile it
in).
There is are several prebuilt versions of *nix as well as RTEMS for the
core on the gaisler website as well. There's a IPv4 stack for RTEMS,
derived from the BSD stack.
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
