On 01/01/13 17:34, Attila Kinali wrote:
On Tue, 1 Jan 2013 11:23:57 -0500
Bob Camp<li...@rtty.us> wrote:
The only problem you may run into with an input capture is that the
72 MHz may be from an internal VCO that's locked to the external clock
source or crystal. Often these micro's don't have VCO's that are as good
a one might hope. You will indeed have less than 1 UI jitter, you may
not have a whole lot less…
What about those uC that use a VCO that runs up at several 100MHz (i've
seen up to 800MHz) and devide it down to what they actually need.
Shouldnt this improve jitter quite considerably?
Many CMOS PLL solutions work like that. For instance, one chip I recall
has a ~2.4 GHz oscillator, divides that down on the output side and then
have input and feedback dividers as well. The benefit is that the tuning
range of the core VCO can be fairly low, and you get decent jitter that way.
For higher rates N-phase oscillators is used, typically 4-phase. Playing
tricks which how those phases are used can keep divider noises down when
doing fractional division rates.
Cheers,
Magnus
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