On Wed, 10 Jun 2015 21:45:33 -0400 Bob Camp <kb...@n1k.org> wrote: > The delay line in an FPGA approach might get you to 20 ps. There is a lot of > hand > waving in the calibration process to get there. ( = figuring out that state A > came before > state B is based on things that are difficult to prove). > > If you do get it calibrated, you then find that it’s sensitive to both supply > voltage and > to temperature. The supply thing you can take care of with a good regulator. > The “shifts > all over the place when you put your thumb on it” T/C is not quite as easy to > deal with. > > A TDC using an R/C and an ADC is a *much* easier way to go.
Just two references on this topic: [1] Is AFAIK the only way to get FPGAs below the intrinsic cell delay (which is varies between a min of 10-20ps and a max of 100-200ps within the same FPGA) And [2] gives an idea how a possible calibration system might work. Attila Kinali [1] "The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay", by Wu, Jinyuan and Shi, Zonghan, 2008 http://dx.doi.org/10.1109/NSSMIC.2008.4775079 [2] "Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator", by Rivior, 2006 http://dx.doi.org/10.1109/ATS.2006.260991 -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.