kb...@n1k.org said: > Since the internal PLLâs have jitter in the 20 to 30 ps RMS range, that > limits a lot of the data you get.
I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs rather than PLLs. They have a long chain of buffers and a giant multiplexor to select the right tap. Does anybody have data on what the "jitter" actually looks like? I'd expect several blurry peaks, with the spacing between peaks being the step size of the delay/mux chain and the blur being wider if there is more random logic. -- These are my opinions. I hate spam.
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