Hi > On Jun 15, 2015, at 11:26 PM, Hal Murray <hmur...@megapathdsl.net> wrote: > > > kb...@n1k.org said: >> Since the internal PLL’s have jitter in the 20 to 30 ps RMS range, that >> limits a lot of the data you get. > > I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs > rather than PLLs.
The jitter on both clock sources looks pretty gaussian. > > They have a long chain of buffers and a giant multiplexor to select the right > tap. > > Does anybody have data on what the "jitter" actually looks like? I'd expect > several blurry peaks, with the spacing between peaks being the step size of > the delay/mux chain and the blur being wider if there is more random logic. The calibration output is a mess … Bob > > > -- > These are my opinions. I hate spam. > > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
