On 1/29/18 3:37 PM, Mark Goldberg wrote:
Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat Long)". There are many sets of register values that will get you the same output frequency and the clock builder may not give you an optimal set for phase noise and spurs. I created a spreadsheet to calculate other sets of values and chose one that worked the best. I just did it through trial and error of the different sets of values I came up with until I found one with low spurs.
We've experienced that here with other PLL chips - For the ADF4108 integer-N PLL, sometimes there's a big difference between R odd and R even (the R is the reference divisor in the fout = fin * (M*B+A)/R
So you wind up fooling around with various combinations of A, B, and R to get the spurs where you want them (or, more commonly, to move them from where you don't want them)
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