> Was considering 16 LVDS receivers and IDELAYS to emulate a single fast > comparator,
I haven't done serious work with FPGAs in 10 or 15 years. That seems like an obvious hack, but it depends on the implementation details inside the FPGA. What's the granularity? How much does it change from chip to chip or over voltage and temperature? Has anybody published any data? ---------- Another possibility is to use trace delays on the PCB. You have a lumped delay line with capacitance from the input pad. This may not be practical for short delays where the bond wires on the chip are not short relative to the trace lengths. -- These are my opinions. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.