Hoi Anders,
On Tue, 14 Jan 2020 08:58:30 +0200
Anders Wallin <anders.e.e.wal...@gmail.com> wrote:
> The obvious way to increase resolution (make the smallest frequency step
> smaller) is to lower the IF.
> I guess the limit is that we don't want the IF to feed-thru the
> phase-detector and PLL all the way to a PN-spur in the output-OCXO.
> My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
> Lowering that by /2 or /4 might be a good idea?
> Other comments and ideas welcome!
Small question about your design choices:
Why do you start with ~400MHz for the DDS ouput frequencies?
Usually, a DDS offers lower noise for a :4 operation than
a D-FF frequency divider. Or is this not the case here?
It might be worthwile to replace DDS2 with a home-brewn one
using an FPGA, a 16bit DAC (e.g. LTC1668) and running it
directly off the 100MHz. The advantage is that you can build
a DDS core that has (almost) arbitrary bit-width and low distortion.
Thus you can decouple the frequency step resolution from the IF frequency
and get another knob you can turn freely. The use of a 16bit, "low speed"
DAC also decreases INL which in turn decreases harmonics (especially even
harmonics and thus flicker noise). The low speed also allows to play
tricks on the DAC word and get lower spurs, especially close in.
(I have an almost ready to use CORDIC implementation you could use, if needed)
And while you do that, you can use a second DAC to produce the 10MHz
signal and thus get lower noise than the MC12080 will give you.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neal Stephenson
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