In message <[EMAIL PROTECTED]> you wrote: > > I don't think this patch is necessary because for all e500v2 core, > setting RSTCR is the right way to reset the board.
Agreed,t hat's how it should wor. But it doesn't on the syscon3 board. > I think you should check board FPGA. I met the similar problem before. > Since FPGA did not correctly route the HRESET_REQ signal, setting RSTCR > did not cause reset. After hardware person fixed the FPGA code, it > worked fine. Ummm... This is on a custom design, the syscon3 board. There is no FPGA there... Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] God made the integers; all else is the work of Man. - Kronecker ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
