On Fri, 2008-05-09 at 19:43 +0200, Wolfgang Denk wrote: > In message <[EMAIL PROTECTED]> you wrote: > > > > I don't think this patch is necessary because for all e500v2 core, > > setting RSTCR is the right way to reset the board. > > Agreed,t hat's how it should wor. But it doesn't on the syscon3 board. > > > I think you should check board FPGA. I met the similar problem before. > > Since FPGA did not correctly route the HRESET_REQ signal, setting RSTCR > > did not cause reset. After hardware person fixed the FPGA code, it > > worked fine. > > Ummm... This is on a custom design, the syscon3 board. There is no > FPGA there... >
There must be some mechanism to reset the board if the HRESET_REQ is connected. If not connected, the board design must accomplish it in another way. Then the platform code should take care of that. York ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
