Hi, thanks in your replay.
I create My own board port(MFT board) . create configuration header and init.S
But In the sdram.c(sdram_init->get_ram_size is 4 thus )func is failed , sdram
is not founded .
I think init.S is something wrong or CFG_MONITOR_BASE is wrong ... .
maybe you can point me to the right direction.
It's my board init.S
_____________________________________________________________________________________________________
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0,
AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0,
AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I
)
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0,
AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0,
AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0,
AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_en
_____________________________________________________________________________________________________
My SDRAM is 128MB mode 3, 13x10(4)
And use external DDR_SDRAM Bank_0(BANKSEL_0)
It's my board configuration header.
_____________________________________________________________________________________________________
Include/configs/mft.h
#define CONFIG_440EP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll *
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH
*/
#define CFG_MONITOR_BASE CFG_FLASH_BASE /* start of monitor
*/
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
#define CFG_ISRAM_BASE CFG_INIT_RAM_ADDR /* internal SRAM
*/
#define CFG_INIT_RAM_END (4 << 10) /* End of used area in RAM
*/
//#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
#define CFG_SDRAM0_TR0 0x410A4012
#undef CONFIG_SDRAM_ECC /* enable ECC support */
#if 1
#define CFG_SDRAM_TABLE { \
{(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4)*/ \
{(128 << 20), 12, 0x000A2001}, /* 128MB mode 2, 13x10(4)*/ \
{(64 << 20), 13, 0x00084001}, /* 64MB mode 3, 13x9(4) */ \
{(64 << 20), 12, 0x00082001}, } /* 64MB mode 2, 13x9(4)
*
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH0 0xFF800000
#define CFG_FLASH1 0xFF000000
#define CFG_FLASH2 0xFE800000
#define CFG_FLASH3 0xFE000000
#define CFG_USB 0xF0000000
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization
*/
//#define CFG_EBC_PB0AP 0x03050200
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /*
BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit *
_____________________________________________________________________________________________________
Best Regards.
Steven.
-----Original Message-----
From: Stefan Roese [mailto:[EMAIL PROTECTED]
Sent: Monday, November 03, 2008 7:11 PM
To: u-boot@lists.denx.de; [EMAIL PROTECTED]
Subject: Re: [U-Boot] new board SDRAM conf
Hi Steven,
On Monday 03 November 2008, 조기성 wrote:
> I Made my board config header, and using yosemite's init.S & u-boot.lds,
> mft.c(Yosemite.c) Only change config header , but it's not working .
You should create your own board port for this custom 440EP board.
> 1. First The difference of my SDRAM configuration is
> *** (PPC440EP supported four external DDR_SDRAM Banks.) ***
> But Our used only external DDR_SDRAM Bank_0(BANKSEL_0) on the New design
> Board.
Yes. I already described how you should handle this DDR initialization in my
last mail. Use the common code (cpu/ppc4xx/sdram.c). You probably need to
change the CONFIG_SYS_SDRAM_TABLE for your board. Take a look at the p3p440.h
header as an example.
BTW: SDRAM configuration is a complex matter. You definitely need to take a
look at the PPC users manual and the SDRAM datasheet for this.
Best regards,
Stefan
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