Hi Stefan. I solved SDRAM problems for your help, when I use CFG_DRAM_TEST , it passed
My bdi2000's configuration is blows WDCR 0x10 0x00000020 ;Select SDRAM0_CFG0 WDCR 0x11 0x34000000 ;CFG0: 32bit, PMU disable WDCR 0x11 0x84000000 ;CFG1: enable SDRA When I Use BID2000, accessing SDRAM with Verify, mm command, It works fine . I think SDRAM0_CFG first is CFG0, and second is CFG1. But in board/amcc/mft.c I used marked code, It's confused me. Long int sdram_init() { //mtsdram (mem_cfg0, 0x34000000); /* confused me */ //mtsdram (mem_cfg1, 0x84000000); mtsdram (mem_cfg1, 0x34000000);/* it works fine */ mtsdram (mem_cfg0, 0x84000000); } I have another problem. cpu/ppc4XX/start.S -> trab_init function has exception error blows LOG MESSAGE. When I debug trap_init , use blr code it succefully returned. maybe you can point me to the right direction. trap_init: lwz r7, GOT(_start_of_vectors) lwz r8, GOT(_end_of_vectors) li r9, 0x100 /* reset vector always at 0x100 */ cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ mflr r4 /* save link register */ 1: lwz r0, 0(r7) stw r0, 0(r9) addi r7, r7, 4 addi r9, r9, 4 cmplw 0, r7, r8 bne 1b /* blr (in this use blr it works Steven) */ Best Regards. Steven. ______________________________LOG MESSAGE_____________________________________________________ U-Boot 1.3.3 (Nov 4 2008 - 18:19:01) CPU: AMCC PowerPC 440EP Rev. C at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz) Bootstrap Option E - Boot ROM Location EBC (16 bits) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: MFT(Multi Function Tester) - AMCC PPC440EP Evaluation Board I2C: ready DTT: 1 FAILED INIT DRAM: 128 MB [init_func_ram]K9 board_add_ram leave [board_init_f]enter [board_init_f:465] [board_init_f:468] Top of RAM usable for U-Boot at: 08000000 Reserving 593k for U-Boot at: 07f6b000 Reserving 136k for malloc() at: 07f49000 Reserving 144 Bytes for Board Info at: 07f48f70 Reserving 56 Bytes for Global Data at: 07f48f38 Stack Pointer at: 07f48f18 [board.c:639] New Stack Pointer is: 07f48f18 [board_init_f:657]addr_sp:0x7f48f18, id:0x7f48f38, addr:0x7f6b000 [board_init_r:679]enter Now running in RAM - U-Boot at: 07f6b000 [board_init_r:706]before watchdog_reset [board_init_r:709]after watchdog [board_init_r:772] [board_init_r:790] Bus Fault @ 0x07f6d7c0, fixup 0x00000000 Machine Check Exception. Caused by (from msr): regs 07f48df8 Data Read PLB Error Data Write PLB Error Machine Check exception is imprecise NIP: 07F6D7C0 XER: 00000000 LR: 07F6D7C0 REGS: 07f48df8 TRAP: 0200 DEAR: CE3EFACB MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 07F6D358 07F48EE8 07F48F38 07F6B000 07F6E6F8 00000001 00000001 07F6D7C0 GPR08: 00000600 00002098 01FCA055 00000000 07F48CF8 27000800 07FB2100 07FEB000 GPR16: 10010000 06110000 00A94200 00638800 24009000 CB010000 00000000 FFFB3B8C GPR24: FFFB2A30 07F48F38 07F6B000 07F6B000 07F9EB8C 07F9DA20 07FB21B4 07F48F70 Call backtrace: 07F6E6F0 07F6D734 machine check __________________________________________________________________________________________ Include/configs/mft.h /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_440EP 1 /* Specifc EP support */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 * #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE //#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */ #define CFG_USB_DEVICE 0x50000000 #define CFG_NVRAM_BASE_ADDR 0x80000000 #define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) #define CFG_BOOT_BASE_ADDR 0xf0000000 /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ #define CFG_ISRAM_BASE CFG_INIT_RAM_ADDR /* internal SRAM */ #define CFG_INIT_RAM_END (4 << 10) /* End of used area in RAM */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ //#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ //#define CFG_SDRAM0_TR0 0x410A4012 #undef CONFIG_SDRAM_ECC /* enable ECC support */ #if 1 // for sdram test #define CFG_DRAM_TEST #define CFG_KBYTES_SDRAM (128 * 1024) #endif _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot