[U-Boot] [PATCH 26/51] strider, hrcon: Reset CAT phy on CON2 module

[Mario Six]

From: Dirk Eibach <dirk.eib...@gdsys.cc>

The phy on the CON2 module needs a defined reset pulse of at least 10 ms
to work reliably.

Signed-off-by: Dirk Eibach <dirk.eib...@gdsys.cc>
Signed-off-by: Mario Six <mario....@gdsys.cc>
---

 board/gdsys/mpc8308/hrcon.c   | 30 ++++++++++++++++++++++++++++++
 board/gdsys/mpc8308/strider.c | 24 ++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index bbe93a3488..d2acd1a677 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -58,6 +58,26 @@ struct {
        u8 addr;
 } hrcon_fans[] = CONFIG_HRCON_FANS;
 
+#ifdef CONFIG_HRCON_DH
+struct {
+       u8 bus;
+       u8 addr;
+       u16 mask;
+} rgmii2_reset[] = { { 0, 0x23, 0x0100},
+                    {10, 0x23, 0x0100},
+                    {11, 0x23, 0x0100},
+                    {12, 0x23, 0x0100} };
+#else
+struct {
+       u8 bus;
+       u8 addr;
+       u16 mask;
+} rgmii2_reset[] = { {0, 0x23, 0x0100},
+                    {6, 0x23, 0x0100},
+                    {7, 0x23, 0x0100},
+                    {8, 0x23, 0x0100} };
+#endif
+
 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
 {
        int res;
@@ -160,6 +180,16 @@ int last_stage_init(void)
                                MCFPGA_RESET_N);
        }
 
+       if (hw_type_cat && ch0_rgmii2_present) {
+               i2c_set_bus_num(rgmii2_reset[0].bus);
+               pca953x_set_val(rgmii2_reset[0].addr, rgmii2_reset[0].mask, 0);
+               pca953x_set_dir(rgmii2_reset[0].addr, rgmii2_reset[0].mask, 0);
+               mdelay(10);
+               pca953x_set_dir(rgmii2_reset[0].addr, rgmii2_reset[0].mask,
+                               rgmii2_reset[0].mask);
+               i2c_set_bus_num(0);
+       }
+
        if (hw_type_cat) {
                uint mux_ch;
                int retval;
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index ac785da8e6..e838913268 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -61,6 +61,17 @@ struct {
        u8 addr;
 } strider_fans[] = CONFIG_STRIDER_FANS;
 
+#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
+struct {
+       u8 bus;
+       u8 addr;
+       u16 mask;
+} sgmii2_reset[] = { { 0, 0x23, 0x0100},
+                    {10, 0x23, 0x0100},
+                    {11, 0x23, 0x0100},
+                    {12, 0x23, 0x0100} };
+#endif
+
 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
 {
        int res;
@@ -178,6 +189,18 @@ int last_stage_init(void)
                                MCFPGA_RESET_N);
        }
 
+#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
+       if (hw_type_cat && ch0_sgmii2_present) {
+               i2c_set_bus_num(sgmii2_reset[0].bus);
+               pca953x_set_val(sgmii2_reset[0].addr, sgmii2_reset[0].mask, 0);
+               pca953x_set_dir(sgmii2_reset[0].addr, sgmii2_reset[0].mask, 0);
+               mdelay(10);
+               pca953x_set_dir(sgmii2_reset[0].addr, sgmii2_reset[0].mask,
+                               sgmii2_reset[0].mask);
+               i2c_set_bus_num(0);
+       }
+#endif
+
        if (hw_type_cat) {
                int retval;
                struct mii_dev *mdiodev = mdio_alloc();
@@ -261,6 +284,7 @@ int last_stage_init(void)
                ch7301_probe(k, false);
                dp501_probe(k, false);
 #endif
+
                if (hw_type_cat) {
                        int retval;
                        struct mii_dev *mdiodev = mdio_alloc();
-- 
2.11.0

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