Hi Stefan, > OK. So you are using 2 chips interleaved on this 16bit bus (one on lower > 8bits > and one on higher 8bits), right? No, I misunderstood yor last e-mail. Our layout is: The flash chip is 16x/8x capable but is configured in 8x mode ( _BYTE pin to GND). Only the low 8 data bits from the processor are connected to the flash data bits. So, I think our layout is chip_width = 8 and port_width = 8. Is it correct?
This is the flinfo report from U-Boot. It's from a Spansion flash board but the Numonyx flash board has the same layout. Bank # 1: CFI conformant FLASH (8 x 8) Size: 16 MB in 128 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x7E2101 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes NOTE: I think the layout you point out could be supported by U-Boot. > > > > I see. Did you check the Linux MTD drivers, if there is a Numonyx special > handling here? > We are working with a 2.4.25 kernel version and the Numonyx is not fully supported (our layout I'm quite sure not). We did some changes to fix it, if you are interested in it I could submit you a patch. Txema _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot