A user exception is triggered by inserting a bralid/brki jump to
"C_BASE_VECTORS+0x8" in the software flow. Because u-boot microblaze code
does not deal with MMU-related features such as user-mode/privileged-mode
separation, there are no code sequences that call into the user exception
handler.
It seems there is no real usecase for having user exception support in
u-boot, so drop the code that installs the nop handler.
Signed-off-by: Ovidiu Panait <ovidiu.pan...@windriver.com>
---
arch/microblaze/cpu/exception.c | 8 -----
arch/microblaze/cpu/start.S | 40 ++-----------------------
board/xilinx/microblaze-generic/Kconfig | 9 ------
3 files changed, 3 insertions(+), 54 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index d3640d3903..1f7c44d1f3 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -63,11 +63,3 @@ void _hw_exception_handler (void)
printf("Return address from exception 0x%x\n", address);
hang();
}
-
-#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
-void _exception_handler (void)
-{
- puts("User vector_exception\n");
- hang();
-}
-#endif
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 645f7cb038..0ea0b78da9 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -97,9 +97,9 @@ clear_bss:
* r5 - relocation offset (zero when setting up vectors before
* relocation, and gd->reloc_off when setting up vectors after
* relocation)
- * - the relocation offset is added to the _exception_handler,
- * _interrupt_handler and _hw_exception_handler symbols to reflect the
- * post-relocation memory addresses
+ * - the relocation offset is added to the _interrupt_handler and
+ * _hw_exception_handler symbols to reflect the post-relocation memory
+ * addresses
*
* Reserve registers:
* r10: Stores little/big endian offset for vectors
@@ -149,40 +149,6 @@ __setup_exceptions:
rsubi r8, r10, 0x6
sh r6, r4, r8
-#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
- /* user_vector_exception */
- swi r2, r4, 0x8 /* user vector exception - imm opcode */
- swi r3, r4, 0xC /* user vector exception - brai opcode */
-
- addik r6, r5, _exception_handler
- sw r6, r1, r0
- /*
- * BIG ENDIAN memory map for user exception
- * 0x8: 0xB000XXXX
- * 0xC: 0xB808XXXX
- *
- * then it is necessary to count address for storing the most
significant
- * 16bits from _exception_handler address and copy it to
- * 0xa address. Big endian use offset in r10=0 that's why is it just
- * 0xa address. The same is done for the least significant 16 bits
- * for 0xe address.
- *
- * LITTLE ENDIAN memory map for user exception
- * 0x8: 0xXXXX00B0
- * 0xC: 0xXXXX08B8
- *
- * Offset is for little endian setup to 0x2. rsubi instruction decrease
- * address value to ensure that points to proper place which is
- * 0x8 for the most significant 16 bits and
- * 0xC for the least significant 16 bits
- */
- lhu r7, r1, r10
- rsubi r8, r10, 0xa
- sh r7, r4, r8
- rsubi r8, r10, 0xe
- sh r6, r4, r8
-#endif
-
/* interrupt_handler */
swi r2, r4, 0x10 /* interrupt - imm opcode */
swi r3, r4, 0x14 /* interrupt - brai opcode */
diff --git a/board/xilinx/microblaze-generic/Kconfig
b/board/xilinx/microblaze-generic/Kconfig
index 117b476f3f..a0af2e9abd 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -38,15 +38,6 @@ config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
default "7.10.d"
-config XILINX_MICROBLAZE0_USR_EXCEP
- bool "MicroBlaze user exception support"
- default y
- help
- Enable this option in order to install the user exception handler
- (_exception_handler routine from arch/microblaze/cpu/exception.c) in
- the exception vector table. The user exception vector is located at
- C_BASE_VECTORS + 0x8 address.
-
config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
bool "MicroBlaze delay slot exception support"
default y
--
2.25.1
