On 5/8/23 20:23, Ralph Siemsen wrote:
On Sun, May 07, 2023 at 06:06:40PM +0200, Marek Vasut wrote:
On 4/24/23 03:15, Ralph Siemsen wrote:
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
The DT comes from Linux kernel, right ? Please include commit ID from
which the DT is imported in the commit message, I suspect that would
be Linux 6.3 commit ID.
Yes, the DT is copied verbatim from Linux. I have updated the commit
message to mention 6.3 and include the hash. (There have been no changes
Thanks
diff --git a/board/schneider/rzn1-snarc/ddr_async.c
b/board/schneider/rzn1-snarc/ddr_async.c
new file mode 100644
index 0000000000..4b4c280e45
--- /dev/null
+++ b/board/schneider/rzn1-snarc/ddr_async.c
Please correct me if I'm wrong, but shouldn't this be in drivers/ram/ ?
I had it there originally, but moved it in v5 of the patch series. There
is a lot of board-specific (or at least architecture-specific) logic in
this file. For example the sequence of steps to setup the clocks and
interconnect, prior to bringing the DDR controller out of reset. This
depends on choices made by the RZ/N1 designers, rather than the CDNS IP
that drivers/ram/cadence is aiming to cover.
Likewise for some board-specific PHY settings, and choices such as
operating in async mode.
I moved it to board-specific directory as an interim step. Hopefully we
can do some consolidation of the multiple CDNS DDR controller
implementations, and then figure out the right way to split things up.
For now this seemed like the less-bad option.
How about putting it into drivers/soc/ ?
