Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5 platform to support the newer controller version with enhanced features.
Key changes: - Remove combophy0 node and associated references as SD6HC doesn't require separate PHY configuration node - Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc" - Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for platform-specific optimizations Hardware configuration updates: - Add voltage regulator support: * sd_emmc_power: Fixed 3.3V regulator for card power supply * sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching - Configure proper reset control with named resets including combophy reset - Add GPIO control via portb pin 3 for voltage switching SD card operation: - Configure for SD card specific operation (no-mmc, cap-sd-highspeed) - Set maximum frequency to 200MHz - Configure timing parameters for SD modes: * Default Speed (DS) and UHS-I SDR12 mode timing: * High Speed and UHS-I SDR25 mode timing: - Add PHY timing delays for optimal signal integrity Signed-off-by: Tanmay Kathpalia <[email protected]> --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 3 +- arch/arm/dts/socfpga_agilex5.dtsi | 29 +++---- .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 77 +++++++++---------- drivers/mmc/sdhci-cadence.c | 1 + 4 files changed, 54 insertions(+), 56 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 35b198b79ef..0f0f457de54 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -698,7 +698,8 @@ }; &mmc { - resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; + resets = <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>, <&rst SDMMC_RESET>; + reset-names = "combophy", "sdmmc-ocp", "sdhc-reset"; }; &porta { diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 7f4266dd5f1..769678af31a 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -303,30 +303,33 @@ status = "disabled"; }; - combophy0: combophy@0 { - #phy-cells = <0>; - phy-type = <1>; - compatible = "cdns,combophy"; - reg = <0x10808000 0x1000>; - resets = <&rst COMBOPHY_RESET>; - reset-names = "reset"; - status = "disabled"; + sd_emmc_power: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-name = "card-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sd_io_1v8_reg: regulator-1p8v { + compatible = "regulator-gpio"; + regulator-name = "sd-bus-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1>, + <3300000 0x0>; }; mmc: mmc0@10808000 { #address-cells = <1>; #size-cells = <0>; - compatible = "cdns,sd4hc"; + compatible = "altr,agilex5-sd6hc", "cdns,sd6hc"; reg = <0x10808000 0x1000>; interrupts = <0 96 4>; - phys = <&combophy0>; - phy-names = "combo-phy"; clocks = <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMMC_CLK>; clock-names = "biu", "ciu"; fifo-depth = <0x800>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; iommus = <&smmu 5>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 938ddb04c04..5a7aa5841e3 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -91,53 +91,46 @@ bootph-all; }; -&mmc { - status = "okay"; - bus-width = <4>; - sd-uhs-sdr50; - cap-mmc-highspeed; +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { bootph-all; }; -&combophy0 { +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { status = "okay"; + + no-mmc; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + bootph-all; - cdns,phy-use-ext-lpbk-dqs = <1>; - cdns,phy-use-lpbk-dqs = <1>; - cdns,phy-use-phony-dqs = <1>; - cdns,phy-use-phony-dqs-cmd = <1>; - cdns,phy-io-mask-always-on = <0>; - cdns,phy-io-mask-end = <5>; - cdns,phy-io-mask-start = <0>; - cdns,phy-data-select-oe-end = <1>; - cdns,phy-sync-method = <1>; - cdns,phy-sw-half-cycle-shift = <0>; - cdns,phy-rd-del-sel = <52>; - cdns,phy-underrun-suppress = <1>; - cdns,phy-gate-cfg-always-on = <1>; - cdns,phy-param-dll-bypass-mode = <1>; - cdns,phy-param-phase-detect-sel = <2>; - cdns,phy-param-dll-start-point = <254>; - cdns,phy-read-dqs-cmd-delay = <0>; - cdns,phy-clk-wrdqs-delay = <0>; - cdns,phy-clk-wr-delay = <0>; - cdns,phy-read-dqs-delay = <0>; - cdns,phy-phony-dqs-timing = <0>; - cdns,hrs09-rddata-en = <1>; - cdns,hrs09-rdcmd-en = <1>; - cdns,hrs09-extended-wr-mode = <1>; - cdns,hrs09-extended-rd-mode = <1>; - cdns,hrs10-hcsdclkadj = <3>; - cdns,hrs16-wrdata1-sdclk-dly = <0>; - cdns,hrs16-wrdata0-sdclk-dly = <0>; - cdns,hrs16-wrcmd1-sdclk-dly = <0>; - cdns,hrs16-wrcmd0-sdclk-dly = <0>; - cdns,hrs16-wrdata1-dly = <0>; - cdns,hrs16-wrdata0-dly = <0>; - cdns,hrs16-wrcmd1-dly = <0>; - cdns,hrs16-wrcmd0-dly = <0>; - cdns,hrs07-rw-compensate = <10>; - cdns,hrs07-idelay-val = <0>; }; &qspi { diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 7d169efa476..6cdb7f95cc5 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -260,6 +260,7 @@ static int sdhci_cdns_probe(struct udevice *dev) static const struct udevice_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc" }, { .compatible = "cdns,sd4hc" }, + { .compatible = "altr,agilex5-sd6hc" }, { .compatible = "cdns,sd6hc" }, { /* sentinel */ } }; -- 2.43.7
