On 15/12/2025 7:01 pm, Tanmay Kathpalia wrote:
Remove GPIO hog configuration for SDIO_SEL pin as it is now handled
through the voltage regulator framework for SD ultra high speed mode
support. The GPIO pin 3 on portb controller is used to control the
level shifter for SD card I/O voltage switching.
The regulator-based approach provides proper voltage switching control
for UHS-I modes (SDR50, SDR104) while maintaining compatibility with
the MMC subsystem's voltage switching protocols.
This reverts commit b0dbc9fcb7dfb7522be25ee205997be2fb5e1bdc.
Signed-off-by: Tanmay Kathpalia <[email protected]>
---
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 11 -----------
configs/socfpga_agilex5_defconfig | 3 ---
2 files changed, 14 deletions(-)
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index d51a9e2ff7f..35b198b79ef 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -681,17 +681,6 @@
bootph-all;
};
-&gpio1 {
- /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe
*/
- portb: gpio-controller@0{
- sdio_sel {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_HIGH>;
- output-low;
- };
- };
-};
-
&i2c0 {
reset-names = "i2c";
};
diff --git a/configs/socfpga_agilex5_defconfig
b/configs/socfpga_agilex5_defconfig
index 64f2f1bf115..799ea910f03 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TEXT_BASE=0x80200000
-CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
@@ -79,8 +78,6 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
Reviewed-by: Tien Fong Chee <[email protected]>
Best regards,
Tien Fong
