On 15/12/2025 7:01 pm, Tanmay Kathpalia wrote:
Add dedicated device tree support for eMMC configuration on the Agilex5
SoCDK board, providing an alternative to the default SD card setup.
Changes to socfpga_agilex5.dtsi:
-
- Configure always-on regulator for stable eMMC operation
New device tree files:
- socfpga_agilex5_socdk_emmc.dts: Main eMMC device tree configuration
* Configure for eMMC operation (no-sd, no-sdio, non-removable)
* Set 8-bit bus width and high speed capability
* Add timing parameters for legacy and SDR modes
* Configure voltage supplies for eMMC power and I/O
* Add fixed 1.8V regulator for eMMC I/O voltage supply
- socfpga_agilex5_socdk_emmc-u-boot.dtsi: U-Boot specific additions
* Include common Agilex5 U-Boot configurations
* Set SPL boot order with eMMC support
* Enable necessary peripherals for boot-time operation
Configuration files:
- configs/socfpga_agilex5_emmc_defconfig: eMMC-specific configuration
* Inherit from base Agilex5 configuration
* Disable GPIO regulator support (not needed for fixed eMMC setup)
* Set eMMC-specific device tree
Build system integration:
- Add socfpga_agilex5_socdk_emmc.dtb target to Makefile
Signed-off-by: Tanmay Kathpalia <[email protected]>
---
arch/arm/dts/Makefile | 1 +
.../socfpga_agilex5_socdk_emmc-u-boot.dtsi | 178 ++++++++++++++++++
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 49 +++++
configs/socfpga_agilex5_emmc_defconfig | 6 +
4 files changed, 234 insertions(+)
create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
create mode 100644 configs/socfpga_agilex5_emmc_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fcad6fb2fc7..4e39c795e1e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -451,6 +451,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex5_socdk.dtb \
+ socfpga_agilex5_socdk_emmc.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi
new file mode 100644
index 00000000000..6aed59f7c19
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions for Agilex5 SocDK eMMC
+ *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include "socfpga_agilex5-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ freeze_br0 = &freeze_controller;
+ };
+
+ soc {
+ freeze_controller: freeze_controller@0x20000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x20000450 0x00000010>;
+ status = "disabled";
+ };
+ };
+
+ /*
+ * Both Memory base address and size default info is retrieved from HW
setting.
+ * Reconfiguration / Overwrite these info can be done with examples
below.
+ *
+ * When LPDDR ECC is enabled, the last 1/8 of the memory region must
+ * be reserved for the Inline ECC buffer.
+ *
+ * Example for memory size with 2GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>;
+ * };
+ *
+ * Example for memory size with 8GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x80000000>;
+ * };
+ *
+ * Example for memory size with 32GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>;
+ * };
+ *
+ * Example for memory size with 512GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>,
+ * <0x88 0x00000000 0x78 0x00000000>;
+ * };
+ *
+ * Example for memory size with 2GB with LPDDR Inline ECC ON:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x70000000>;
+ * };
+ *
+ * Example for memory size with 8GB with LPDDR Inline ECC ON:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x40000000>;
+ * };
+ */
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory";
+ };
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ bootph-all;
+ /delete-property/ cdns,read-delay;
+};
+
+&flash1 {
+ bootph-all;
+};
+
+&i3c0 {
+ bootph-all;
+};
+
+&i3c1 {
+ bootph-all;
+};
+
+&gpio1 {
+ portb: gpio-controller@0 {
+ bootph-all;
+ };
+};
+
+&sd_emmc_power {
+ bootph-all;
+};
+
+&emmc_io_1v8_reg {
+ bootph-all;
+};
+
+&mmc {
+ bootph-all;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&nand {
+ status = "disabled";
+ bootph-all;
+};
+
+&timer0 {
+ bootph-all;
+};
+
+&timer1 {
+ bootph-all;
+};
+
+&timer2 {
+ bootph-all;
+};
+
+&timer3 {
+ bootph-all;
+};
+
+&watchdog0 {
+ bootph-all;
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac0_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac0_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac2_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&binman {
+ /delete-node/ kernel;
+};
+#endif
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
new file mode 100644
index 00000000000..f6848c373cd
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include "socfpga_agilex5_socdk.dts"
+
+/ {
+ soc {
+ emmc_io_1v8_reg: regulator-fixed-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "emmc-io-power";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mmc {
+ status = "okay";
+
+ no-sd;
+ no-sdio;
+ disable-wp;
+ non-removable;
+ cap-mmc-highspeed;
+
+ bus-width = <8>;
+ vmmc-supply = <&sd_emmc_power>;
+ vqmmc-supply = <&emmc_io_1v8_reg>;
+ max-frequency = <200000000>;
+
+ /* eMMC legacy mode timing configuration */
+ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
+ cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>;
+ cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
+ cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
+
+ /* eMMC SDR mode timing configuration */
+ cdns,phy-dqs-timing-delay-emmc-sdr = <0x780001>;
+ cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x81a40040>;
+ cdns,phy-dll-slave-ctrl-emmc-sdr = <0x00000000>;
+ cdns,phy-dq-timing-delay-emmc-sdr = <0x10000001>;
+ cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0x1800c>;
+ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
+ cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
+ cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
+};
diff --git a/configs/socfpga_agilex5_emmc_defconfig
b/configs/socfpga_agilex5_emmc_defconfig
new file mode 100644
index 00000000000..9254ab92e0c
--- /dev/null
+++ b/configs/socfpga_agilex5_emmc_defconfig
@@ -0,0 +1,6 @@
+#include <configs/socfpga_agilex5_defconfig>
+
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc"
+# CONFIG_SPL_DM_REGULATOR_GPIO is not set
+# CONFIG_DM_REGULATOR_GPIO is not set
+# CONFIG_SPL_DWAPB_GPIO is not set
Reviewed-by: Tien Fong Chee <[email protected]>
Best regards,
Tien Fong
