On Tue, Dec 16, 2025 at 02:38:35PM +0800, [email protected] wrote:
> From: Alice Guo <[email protected]>
>
> Extract USB PHY initialization code from ehci-mx6.c into a new function
> ehci_mx6_phy_init() that can be shared with the ChipIdea UDC driver.
>
> Signed-off-by: Alice Guo <[email protected]>
> ---
> drivers/usb/host/ehci-mx6.c | 73
> ++++++++++++++++++++++++++++++++++++++++++++-
> include/usb/ci_udc.h | 9 ++++++
> 2 files changed, 81 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> index 03ff4ce10d5..52f14e6eca0 100644
> --- a/drivers/usb/host/ehci-mx6.c
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -12,6 +12,7 @@
> #include <asm/global_data.h>
> #include <linux/compiler.h>
> #include <linux/delay.h>
> +#include <usb/ci_udc.h>
> #include <usb/ehci-ci.h>
> #include <asm/io.h>
> #include <asm/arch/imx-regs.h>
> @@ -168,6 +169,54 @@ static void __maybe_unused
> usb_power_config_mx7ulp(void *usbphy) { }
> #endif
>
> +#if defined(CONFIG_IMX8)
> +static void usb_power_config_imx8(void __iomem *usbphy_base)
> +{
> + struct usbphy_regs __iomem *usbphy = (struct usbphy_regs __iomem
> *)usbphy_base;
> +
> + if (!is_imx8())
> + return;
> +
> + int timeout = 1000000;
> +
> + if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
> + /* Enable the regulator first */
> + writel(PLL_USB_REG_ENABLE_MASK,
> + &usbphy->usb1_pll_480_ctrl_set);
> +
> + /* Wait at least 25us */
> + udelay(25);
> +
> + /* Enable the power */
> + writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
> +
> + /* Wait lock */
> + while (timeout--) {
> + if (readl(&usbphy->usb1_pll_480_ctrl) &
> + PLL_USB_LOCK_MASK)
> + break;
> + udelay(10);
> + }
We have readX_poll_timeout() defined in include/linux/iopoll.h, I think
it could simplify the code here.
> + if (timeout <= 0) {
> + /* If timeout, we power down the pll */
> + writel(PLL_USB_PWR_MASK,
> + &usbphy->usb1_pll_480_ctrl_clr);
> + return;
> + }
> + }
> +
> + /* Clear the bypass */
> + writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
> +
> + /* Enable the PLL clock out to USB */
> + writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
> + &usbphy->usb1_pll_480_ctrl_set);
> +}
Regards,
Yao Zi
