Convert all parent clock arrays to use struct mtk_parent. This will allow us to simplify core code later by having only one possible data type for mux parent arrays.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt8365.c | 522 +++++++++++++++++++------------------- 1 file changed, 261 insertions(+), 261 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 2b1703e7203..41dd2479c5a 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -298,347 +298,347 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2 -}; - -static const int mem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_MMPLL_D2, -}; - -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), +}; + +static const struct mtk_parent mem_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), +}; + +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_192M_D8, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_USB20_192M_D4, - CLK_TOP_UNIVPLL2_D32, - CLK_TOP_USB20_192M_D16, - CLK_TOP_USB20_192M_D32, +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_USB20_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), + TOP_PARENT(CLK_TOP_USB20_192M_D16), + TOP_PARENT(CLK_TOP_USB20_192M_D32), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent msdc50_0_hc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent msdc50_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent msdc30_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int disp_pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent disp_pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent dxcc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 +static const struct mtk_parent ssusb_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int senif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent senif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int aes_fde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent aes_fde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_LVDSPLL_D2, - CLK_TOP_LVDSPLL_D4, - CLK_TOP_LVDSPLL_D8, - CLK_TOP_LVDSPLL_D16 +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_LVDSPLL_D2), + TOP_PARENT(CLK_TOP_LVDSPLL_D4), + TOP_PARENT(CLK_TOP_LVDSPLL_D8), + TOP_PARENT(CLK_TOP_LVDSPLL_D16), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8 +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), }; -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_cpm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int apu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_APUPLL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4 +static const struct mtk_parent apu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_APUPLL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), - MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), - MUX_GATE(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), - MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), - MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), - MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), - MUX_GATE(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), - MUX_GATE(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), - MUX_GATE(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), - MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), + MUX_GATE_MIXED(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), - MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), - MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), - MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), + MUX_GATE_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), - MUX_GATE(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), - MUX_GATE(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), + MUX_GATE_MIXED(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), - MUX_GATE(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), - MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), - MUX_GATE(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), + MUX_GATE_MIXED(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), - MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), - MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), - MUX_GATE(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), + MUX_GATE_MIXED(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), - MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), - MUX_GATE(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), - MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), + MUX_GATE_MIXED(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), /* CLK_CFG_9 */ - MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), - MUX_GATE(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), - MUX_GATE(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), - MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), + MUX_GATE_MIXED(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), /* CLK_CFG_10 */ - MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), - MUX_GATE(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), - MUX_GATE(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), - MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), + MUX_GATE_MIXED(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), + MUX_GATE_MIXED(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), + MUX_GATE_MIXED(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), + MUX_GATE_MIXED(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), }; /* topckgen cg */ -- 2.43.0
