On 10/04/2012 07:14 PM, Scott Wood wrote:
> On 10/04/2012 02:36:34 AM, Stefan Roese wrote:
>> On 10/02/2012 10:08 PM, Scott Wood wrote:
>>>>>> +void __noreturn jump_to_image_linux(void *arg)
>>>>>> +{
>>>>>> + debug("Entering kernel arg pointer: 0x%p\n", arg);
>>>>>> + typedef void (*image_entry_arg_t)(void *, ulong r4,
>> ulong r5,
>>>>>> ulong r6,
>>>>>> + ulong r7, ulong r8,
>> ulong r9)
>>>>>> + __attribute__ ((noreturn));
>>>>>> + image_entry_arg_t image_entry =
>>>>>> + (image_entry_arg_t)spl_image.entry_point;
>>>>>> +
>>>>>> + image_entry(arg, 0, 0, EPAPR_MAGIC,
>> CONFIG_SYS_BOOTMAPSZ, 0, 0);
>>>>>> +}
>>>>>
>>>>> At what point does the image get cache-flushed?
>>>>
>>>> Not at all right now. MPC5200 has dcache disabled, at least in the
>>>> SPL.
>>>> Other PowerPC architectures might add a cache flush here if needed
>> at
>>>> some time. Okay?
>>>
>>> Or they might forget to do so and have weird bugs.
>>>
>>> Why not just call flush_cache() on the image now? Non-SPL does
>> this in
>>> common code, not even PPC-specific.
>>
>> Okay, probably better to add this code now. But shouldn't we add this
>> code to the common SPL framework code then? Right before calling
>> jump_to_image_linux()?
>
> Sure, I didn't mean it should go here (it needs to be somewhere that
> knows the image start/end, not just the entry point). This is just the
> patch that prompted me to ask the question.
I see.
Tom, whats your input on this? Do you see any problems about putting a
flush_cache() into the common SPL framework code? Are any of the ARM
platforms currently using this framework already running with d-cache
enabled?
Should I post a patch?
Thanks,
Stefan
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