The Flipper One display bus has no MISO wire; the pin is the
end-of-frame GPIO. Patch 1 maps spi-{tx,rx}-bus-width = <0> to
SPI_NO_TX/SPI_NO_RX and validates transfers against the bits in
dm_spi_xfer(). Patch 2 has the Rockchip driver pick its transfer mode
from them so the unused FIFO stays out of the transfer. Background is
in the v2 cover letter:https://lore.kernel.org/all/[email protected]/ Changes in v4, both from the comment discussion with Quentin: - toread comment cut down to the one factual sentence - the comment above rkspi_wait_till_not_busy() now says why the wait matters: the TX FIFO can still hold unsent data and disabling the controller clears the FIFOs - patch 1 unchanged, carries the Acked-by Cole Munz (2): spi: Handle spi-{tx,rx}-bus-width 0 as SPI_NO_TX/SPI_NO_RX spi: rockchip: skip the unused FIFO direction on a one-wire device drivers/spi/rk_spi.c | 33 ++++++++++++++++++++++++++------- drivers/spi/spi-uclass.c | 16 ++++++++++++++++ include/spi.h | 2 ++ test/dm/spi.c | 39 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 83 insertions(+), 7 deletions(-) base-commit: 527115ef6783cec49e5610c523c124b399011361 -- 2.55.0
