On Wed, Aug 26, 2026 at 04:11:57AM +0530, AK Sharma wrote: > Add the TPL and SPL stages for the EN75xx. The TPL brings up the cache > and SoC straps, runs the vendor DDR calibration stage from flash via the > early SFC (serial-flash controller) reader, then the SPL loads U-Boot > proper. > > The DDR calibration stage is a vendor artifact read from flash at boot > and is not shipped in-tree; see arch/mips/mach-en75xx/README.ddr-blob for > how to obtain it and its checksums. > > Signed-off-by: AK Sharma <[email protected]> > --- > arch/mips/mach-en75xx/README.ddr-blob | 21 ++
Documentation needs to be in rST format and under doc/ (and then make KDOC_WERROR=1 htmldocs must be clean). -- Tom
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