On 8/26/26 10:12 AM, Frieder Schrempf wrote:
[...]
I'm not sure, but even if it would work, it would require several
separate init attempts only to read the IDs
Why ? Init the bus in slowest mode with widest bus settings, then try
MRRD on all available DRAM chips, then figure out which ones report
valid IDs and which ones fail the MRd .
As far as I can see this doesn't work. If we use the widest bus setting
(CsPresent=0x3) on a single rank module, the training fails and the DDR
remains in a state where the MR read doesn't work yet.
Do you need training to read the IDs ? Simply force-use the slowest bus
mode (100 MTps iirc), the training is only relevant for the high-speed
modes.
[...]
