On 8/27/26 3:35 PM, Frieder Schrempf wrote:
On 26.08.26 14:24, Marek Vasut wrote:
On 8/26/26 10:12 AM, Frieder Schrempf wrote:
[...]
I'm not sure, but even if it would work, it would require several
separate init attempts only to read the IDs
Why ? Init the bus in slowest mode with widest bus settings, then try
MRRD on all available DRAM chips, then figure out which ones report
valid IDs and which ones fail the MRd .
As far as I can see this doesn't work. If we use the widest bus setting
(CsPresent=0x3) on a single rank module, the training fails and the DDR
remains in a state where the MR read doesn't work yet.
Do you need training to read the IDs ? Simply force-use the slowest bus
mode (100 MTps iirc), the training is only relevant for the high-speed
modes.
I don't see any existing code path for any i.MX with DDR4 that doesn't
do the training before accessing MR registers. Do you have any
references or examples? Do you have any sources for the claim that the
training is only relevant for the high-speed modes? I couldn't find
anything that supports this.
What happens if you simply skip the DDR training, return 0 from
ddr_cfg_phy() ?
Also I would assume that doing the MRRD on an unused CS would give me
back some arbitrary random values. While I could interpret an unknown
value as "rank/cs not present", I don't think its reliable enough. Or do
you know of any error condition being reported for failed MRRD?
Try it and see what happens ?
