Hi Dave,
On 12:32 Tue 06 Oct , Dave Klotz wrote:
> The UTMI PHY at c0a30000 ("spacemit,k1-usb2-phy") feeds the K1's DWC3
> USB 3 controller. Port the Linux driver: enable the PHY clock, program
> the PLL divider for the 24 MHz reference, wait for the PLL, then release
> the PHY's resets and enable its clocks, the HS TX clock and the
> automatic host-disconnect clear.
>
> The divider has to be written before the PLL is polled. On the OrangePi
> R2S under FreeBSD, a driver that polled first and never wrote it left
> the PLL stopped: the clock enables did not latch (0x60ef read back as
> 0x60e9), the PHY gave the controller no UTMI clock and the xHCI reset
> (USBCMD.HCRST) never completed. Warn if the enables do not latch.
>
> Also apply the vendor's HS DAC current setting (+15 %), which the
> FreeBSD driver that runs the R2S port does.
>
> Signed-off-by: Dave Klotz <[email protected]>
> ---
> MAINTAINERS | 1 +
> drivers/phy/spacemit/Kconfig | 9 ++
> drivers/phy/spacemit/Makefile | 1 +
> drivers/phy/spacemit/phy-k1-usb2.c | 173 +++++++++++++++++++++++++++++
> 4 files changed, 184 insertions(+)
> create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c
>
..
> +
> +static const struct udevice_id spacemit_usb2phy_ids[] = {
> + { .compatible = "spacemit,k1-usb2-phy" },
Since K3 SoC share this IP with minor difference which we don't
care in U-Boot, and also I've tested, it works fine on K3 SoC,
so please add in next version, thanks
{ .compatible = "spacemit,k3-usb2-phy" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(spacemit_k1_usb2_phy) = {
> + .name = "spacemit_k1_usb2_phy",
> + .id = UCLASS_PHY,
> + .of_match = spacemit_usb2phy_ids,
> + .probe = spacemit_usb2phy_probe,
> + .ops = &spacemit_usb2phy_ops,
> + .priv_auto = sizeof(struct spacemit_usb2phy),
> +};
>
--
Yixun Lan (dlan)
