From: Frieder Schrempf <[email protected]> The power up procedure in ddr_init() makes sure the DDRMIX power domain is mapped to the A53 and powered by writing to the GPC registers at hard coded addresses. These match the GPC layout of i.MX8MQ, i.MX8MM and i.MX8MN, but not the one of i.MX8MP. There, the domain mapping is at offset 0x1cc and the power up request register at offset 0xd8 with the DDRMIX at bit 19. On i.MX8MP the procedure currently writes to registers that are not related to the DDRMIX at all, such as GPC_GPC_LPCR_CM4_AD at 0xec.
This goes unnoticed, as the DDRMIX is already powered on after reset, but it prevents powering the domain up again after it has been turned off. Add defines for the GPC registers and bits of the DDRMIX domain, with the i.MX8MP values taken from TF-A and the Linux gpcv2 driver and verified against the i.MX8MP reference manual, and use them instead of the hard coded addresses. Assisted-by: LLM Signed-off-by: Frieder Schrempf <[email protected]> --- drivers/ddr/imx/imx8m/ddr_init.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index e9209ce8b61..0706face14a 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -10,6 +10,19 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +/* GPC registers for the DDRMIX (DDR1) power domain */ +#ifdef CONFIG_IMX8MP +#define GPC_PGC_CPU_MAPPING 0x1cc +#define GPC_PGC_CPU_MAPPING_ALL 0x003fffff +#define GPC_PU_PGC_SW_PUP_REQ 0x0d8 +#define GPC_DDR1_SW_Pxx_REQ BIT(19) +#else +#define GPC_PGC_CPU_MAPPING 0x0ec +#define GPC_PGC_CPU_MAPPING_ALL 0x0000ffff +#define GPC_PU_PGC_SW_PUP_REQ 0x0f8 +#define GPC_DDR1_SW_Pxx_REQ BIT(5) +#endif + static unsigned int g_cdd_rr_max[4]; static unsigned int g_cdd_rw_max[4]; static unsigned int g_cdd_wr_max[4]; @@ -333,8 +346,8 @@ int ddr_init(struct dram_timing_info *dram_timing) CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* disable iso */ - reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + reg32_write(GPC_BASE_ADDR + GPC_PGC_CPU_MAPPING, GPC_PGC_CPU_MAPPING_ALL); + setbits_le32(GPC_BASE_ADDR + GPC_PU_PGC_SW_PUP_REQ, GPC_DDR1_SW_Pxx_REQ); initial_drate = dram_timing->fsp_msg[0].drate; /* default to the frequency point 0 clock */ -- 2.55.0
