From: Frieder Schrempf <[email protected]> The OSM-S i.MX8MP probes its DDR size by initializing the 8GB configuration first and repeating ddr_init() with the 4GB configuration if the 8GB can not be addressed. Accessing the DRAM after the second ddr_init() used to freeze the SoC, which was worked around by an additional short size check before the second init.
The actual cause was that ddr_init() did not return the DDRMIX to its power-on state before repeating the initialization. Now that this is fixed, the workaround is not needed anymore. Remove it. Signed-off-by: Frieder Schrempf <[email protected]> --- board/kontron/osm-s-mx8mp/spl.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/board/kontron/osm-s-mx8mp/spl.c b/board/kontron/osm-s-mx8mp/spl.c index 20fd960243b..04a43192cb5 100644 --- a/board/kontron/osm-s-mx8mp/spl.c +++ b/board/kontron/osm-s-mx8mp/spl.c @@ -68,20 +68,6 @@ static void spl_dram_init(void) size = 8; // assume 4GB if ddr_init() succeeds but 8GB can not be addressed else if (!ret) { - /* - * For some strange, unknown reason freezes are occurring if we run - * check_ram_available() after the second call to ddr_init(). This - * doesn't seem to be an issue with caching as it also happens with - * caches disable. The workaround that does the trick is accessing the - * DDR areas once more before calling ddr_init() and - * check_ram_available() again. This can be done by rerunning the size - * check on the first few bytes of the DDR. - * On the other hand this breaks the 1GB DDR init, but we can skip this - * as the 1GB is single rank and the training fails. We can detect that - * by checking the return code of ddr_init(). - */ - check_ram_available(256); - /* * Overwrite some values to comply with the 4GB DDR. */ -- 2.55.0
