The generic counter shared by the Cortex-A720AE and Cortex-R52 cores is stopped at reset. With U-Boot as the first stage on the RSIP-M, nothing starts it before the Cortex-R52 cores are released, so their timers never advance and a timed wait such as a Zephyr k_sleep() blocks forever.
Program the counter frequency and enable it before any other initialization, through the RSIP-M alias of the counter frame. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Clément Le Goffic <[email protected]> --- Start the generic counter from the RSIP-M U-Boot on R-Car X5H. --- board/renesas/common/gen5-cm33.c | 14 ++++++++++++++ configs/r8a78000_ironhide_cm33_defconfig | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index f532daa16d5d..1837283c2bef 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -58,6 +58,10 @@ DECLARE_GLOBAL_DATA_PTR; #define RSIP_CTL_PROT0PS (RSIP_CTL_BASE + 0x844) #define RSIP_CTL_PROT0PS_ERR BIT(0) +#define CNTCR_BASE 0xbc000000 +#define CNTCR_EN BIT(0) +#define CNTFID0 (CNTCR_BASE + 0x20) + #define SYSSS_BASE 0xc1320000 #define SYSSS_MODE1 (SYSSS_BASE + 0x1010) #define SYSSS_MODE1_MASK GENMASK(11, 0) @@ -1280,11 +1284,21 @@ static void gic720ae_init(void) writel(1, GIC720AE_GICR_VIEWR(i)); /* View 1 */ } +/** + * generic_counter_start() - Start the generic counter shared by all cores + */ +static void generic_counter_start(void) +{ + writel(CONFIG_SYS_CLK_FREQ, CNTFID0); + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + /** * mach_cpu_init() - Initialize hardware and start other cores */ int mach_cpu_init(void) { + generic_counter_start(); mfis_unprotect(); pfc_set_avs_pinmux(); mdlc_mpg_start(); diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig index 3f09a7c25568..37d700096ff3 100644 --- a/configs/r8a78000_ironhide_cm33_defconfig +++ b/configs/r8a78000_ironhide_cm33_defconfig @@ -65,7 +65,7 @@ CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_SKIP_RELOCATE=y CONFIG_SYS_BARGSIZE=2048 CONFIG_SYS_BOOT_GET_CMDLINE=y -CONFIG_SYS_CLK_FREQ=16666666 +CONFIG_SYS_CLK_FREQ=1066666667 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_SYS_FLASH_PROTECTION=y --- base-commit: 8649a54d301a4d0ac526324c7a7ad2574939ff27 change-id: 20261026-clegoffic-gen5-generic-counter-cd7f953b6d69 Best regards, -- Clément Le Goffic <[email protected]>
