Hi Marek,
Thanks for the review,
On 10/26/26 11:18 PM, Marek Vasut wrote:
On 10/26/26 4:36 PM, Clément Le Goffic wrote:
The generic counter shared by the Cortex-A720AE and Cortex-R52 cores is
stopped at reset. With U-Boot as the first stage on the RSIP-M, nothing
starts it before the Cortex-R52 cores are released, so their timers never
advance and a timed wait such as a Zephyr k_sleep() blocks forever.
Program the counter frequency and enable it before any other
initialization, through the RSIP-M alias of the counter frame.
Why is U-Boot on RSIP supposed to be doing this, why is Zephyr on the
CR52 not doing it when it needs that counter ?
In the Renesas SDK it is the Gen5_IPL that start it. U-boot replaces
that stage.
From the manual "Set bit 0 in CNTCR to 1 to start the Generic Counter
when the CPU is placed in the secure mode."
By default R52 is in secure mode but this can change by changing AxPROT[1].
This mean a zephyr running on a R52 not in secure mode can't start it.
Does anything on the RSIP or CA720 depend on this counter ?
RSIP-M: no
A720: components after BL31 depends on it and actually it is already
started by TFA BL31 here [1].
When you don't boot BL31 it is not started. It is in that case that we
had an issue.
What is the problem you really observe ?
As said in the commit message a Zephyr k_sleep() blocks forever when it
is not started.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Clément Le Goffic <[email protected]>
---
Start the generic counter from the RSIP-M U-Boot on R-Car X5H.
What is this ^ sentence doing here below --- ?
That's where b4 land the cover letter for single patch.
This part is ignored when the patch is applied.
---
board/renesas/common/gen5-cm33.c | 14 ++++++++++++++
configs/r8a78000_ironhide_cm33_defconfig | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/
gen5-cm33.c
index f532daa16d5d..1837283c2bef 100644
--- a/board/renesas/common/gen5-cm33.c
+++ b/board/renesas/common/gen5-cm33.c
@@ -58,6 +58,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define RSIP_CTL_PROT0PS (RSIP_CTL_BASE + 0x844)
#define RSIP_CTL_PROT0PS_ERR BIT(0)
+#define CNTCR_BASE 0xbc000000
+#define CNTCR_EN BIT(0)
+#define CNTFID0 (CNTCR_BASE + 0x20)
+
#define SYSSS_BASE 0xc1320000
#define SYSSS_MODE1 (SYSSS_BASE + 0x1010)
#define SYSSS_MODE1_MASK GENMASK(11, 0)
@@ -1280,11 +1284,21 @@ static void gic720ae_init(void)
writel(1, GIC720AE_GICR_VIEWR(i)); /* View 1 */
}
+/**
+ * generic_counter_start() - Start the generic counter shared by all
cores
+ */
+static void generic_counter_start(void)
+{
+ writel(CONFIG_SYS_CLK_FREQ, CNTFID0);
+ setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
/**
* mach_cpu_init() - Initialize hardware and start other cores
*/
int mach_cpu_init(void)
{
+ generic_counter_start();
mfis_unprotect();
pfc_set_avs_pinmux();
mdlc_mpg_start();
diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/
r8a78000_ironhide_cm33_defconfig
index 3f09a7c25568..37d700096ff3 100644
--- a/configs/r8a78000_ironhide_cm33_defconfig
+++ b/configs/r8a78000_ironhide_cm33_defconfig
@@ -65,7 +65,7 @@ CONFIG_SIMPLE_BUS_CORRECT_RANGE=y
CONFIG_SKIP_RELOCATE=y
CONFIG_SYS_BARGSIZE=2048
CONFIG_SYS_BOOT_GET_CMDLINE=y
-CONFIG_SYS_CLK_FREQ=16666666
+CONFIG_SYS_CLK_FREQ=1066666667
Why did the frequency change ? (that really has to be explained in the
commit message)
Manual: "The generic timer counts up by H'10 every clock edge of
SASYNCD1_RT_MAIN clock continuously."
SASYNCD1_RT_MAIN = 66.666667 MHz
66.666667 MHz × 16 = 1066.666667 MHz -> 1066666667
I'll modify the commit message.
[1]:
https://elixir.bootlin.com/arm-trusted-firmware/v2.15.0/source/plat/renesas/rcar_gen5/bl31_plat_setup.c#L171
Best regards,
Clément
