On Thu, Oct 29, 2026 at 01:00:07PM +0530, KR Sowmiya wrote: > Add support for: > > Reading DDR training data from eMMC during Shikra boot flow and sending it to > QcLIB via interface table. > > Saving DDR training data in eMMC when QcLIB performs DDR training and > sends the data via interface table. > > Signed-off-by: KR Sowmiya <[email protected]> > --- > arch/arm/mach-snapdragon/Kconfig | 66 +++++++++ > arch/arm/mach-snapdragon/board_spl.c | 126 ++++++++++++++++++ > arch/arm/mach-snapdragon/include/mach/qclib.h | 3 + > arch/arm/mach-snapdragon/include/mach/spl.h | 2 + > board/qualcomm/shikra/spl-shikra.c | 35 ++++- > 5 files changed, 225 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/mach-snapdragon/Kconfig > b/arch/arm/mach-snapdragon/Kconfig > index 9e23d6d8948..92bce79b25c 100644 > --- a/arch/arm/mach-snapdragon/Kconfig > +++ b/arch/arm/mach-snapdragon/Kconfig > @@ -93,6 +93,72 @@ config QCOM_XBL_SEC_ELF > The image is copied to the build output as xbl_sec.elf and embedded > by the platform SPL linker script as a Qualcomm XBL-sec segment. > > +config QCOM_DDR_TRAINING_SUPPORTED > + bool "Enable DDR training data save/restore support in SPL" > + depends on SPL
Since both of the valid options here depend on something else, this also needs to depend on one of them being set. -- Tom
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