Added support for DDR training for Shikra. Following are added: Reading DDR training data from eMMC during Shikra boot flow and sending it to QcLIB via interface table. Saving DDR training data in eMMC when QcLIB performs DDR training and sends the data via interface table.
Depends on: https://lore.kernel.org/u-boot/[email protected]/ Changes in v2 - Addressed similar review comments received in https://lore.kernel.org/u-boot/[email protected]/ KR Sowmiya (1): DDR training: enabled DDR training for Shikra SPL arch/arm/mach-snapdragon/Kconfig | 66 +++++++++ arch/arm/mach-snapdragon/board_spl.c | 126 ++++++++++++++++++ arch/arm/mach-snapdragon/include/mach/qclib.h | 3 + arch/arm/mach-snapdragon/include/mach/spl.h | 2 + board/qualcomm/shikra/spl-shikra.c | 35 ++++- 5 files changed, 225 insertions(+), 7 deletions(-) -- 2.43.0
