On Fri, Oct 30, 2026 at 09:57:41 +0100, Steffen Dirkwinkel wrote:
> From: Steffen Dirkwinkel <[email protected]>
>
> Running through spl without the dcache is very slow, especially when
> hashing or checking signatures.
>
> Time from the SPL banner to entering BL31 on an MT8370 module loading a
> 2.7 MB FIT with SHA-256 hashes from SPI NOR, two boots each:
>
> FIT caches off caches on
> unsigned 864.0 / 864.3 ms 95.8 / 95.8 ms
> RSA-3072 signature 1903.3 / 1903.8 ms 142.0 / 142.0 ms
>
> Signed-off-by: Steffen Dirkwinkel <[email protected]>
> ---
> arch/arm/mach-mediatek/mt8188/init.c | 14 ++++++++++++++
> arch/arm/mach-mediatek/spl.c | 7 +++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/mach-mediatek/mt8188/init.c
> b/arch/arm/mach-mediatek/mt8188/init.c
> index b2cdec8c2189..2e6aa041c38f 100644
> --- a/arch/arm/mach-mediatek/mt8188/init.c
> +++ b/arch/arm/mach-mediatek/mt8188/init.c
> @@ -6,6 +6,7 @@
> * Chris-QJ Chen <[email protected]>
> */
>
> +#include <cpu_func.h>
> #include <asm/global_data.h>
> #include <asm/system.h>
> #include <dm/uclass.h>
> @@ -47,3 +48,16 @@ int print_cpuinfo(void)
> printf("CPU: MediaTek MT8188\n");
> return 0;
> }
> +
> +#if IS_ENABLED(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
> +/* Early page tables, in DRAM unused by SPL and by U-Boot before relocation
> */
> +#define MT8188_EARLY_TLB_ADDR 0x4e000000
Could we use an explicitly allocated/aligned buffer for the early tables
instead of 0x4e000000? That address works with the current layout, but
nothing reserves it against other image loads.
> +
> +/* Initialize the MMU and activate the data cache in SPL */
> +void mtk_spl_enable_caches(void)
> +{
> + gd->arch.tlb_addr = MT8188_EARLY_TLB_ADDR;
> + gd->arch.tlb_size = PGTABLE_SIZE;
> + dcache_enable();
> +}
> +#endif
With CONFIG_CMO_BY_VA_ONLY=y, the baseline reaches the console, but
this patch stops before BL31. SPL leaves gd->ram_base/ram_size unset, so
VA-based cache flushing skips RAM. Could we handle this mode, or leave
early caching disabled for it?
> diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c
> index 125ebcd784fe..8073101e3ef6 100644
> --- a/arch/arm/mach-mediatek/spl.c
> +++ b/arch/arm/mach-mediatek/spl.c
> @@ -14,10 +14,17 @@ __weak int mtk_soc_early_init(void)
> return 0;
> }
>
> +__weak void mtk_spl_enable_caches(void)
> +{
> +}
> +
> void board_init_f(ulong dummy)
> {
> int ret;
>
> + /* enable caches early */
> + mtk_spl_enable_caches();
> +
The BL31 path already disables D-cache/MMU, but jump_to_image() does
not, so this patch is in general fine if we are jumping to BL31 but it
is not if we directly jump to BL33 for example.
I tried a direct jump to a proper U-Boot from SPL and indeed both remain
enabled with this patch, whereas the baseline hands over with both
disabled. Could we cover the direct handoff too?
> ret = spl_early_init();
> if (ret)
> hang();
>
> --
> 2.56.0
>
