Enable the clock, reset, I2C and EEPROM support needed to read the DDR
part number, along with the K3 RAM driver for LPDDR5 initialization.
Place SPL at 0xc0801000, leaving 4 KiB at the start of SRAM for the boot
image header. Limit SPL to 256 KiB and allow another 64 KiB for the DDR
PMU firmware, placing BSS after this reserved area at 0xc0851000.
Reserve 4 KiB for BSS and set the initial stack top to the end of the
512 KiB SRAM window at 0xc0880000.
0xc0800000 +-------------------------+
| smtimage header | 4 KiB
0xc0801000 +-------------------------+
| SPL + DDR PMU firmware | 320 KiB budget
0xc0851000 +-------------------------+
| BSS | 4 KiB reserved
0xc0852000 +-------------------------+
| Free space |
| GD, early heap, stack |
0xc0880000 +-------------------------+ <- stack top
Signed-off-by: Junhui Liu <[email protected]>
---
configs/spacemit_k3_defconfig | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/configs/spacemit_k3_defconfig b/configs/spacemit_k3_defconfig
index f49442951c8..c2975759b51 100644
--- a/configs/spacemit_k3_defconfig
+++ b/configs/spacemit_k3_defconfig
@@ -8,8 +8,17 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xa0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="spacemit/k3-pico-itx"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SPL_STACK=0xc0880000
+CONFIG_SPL_TEXT_BASE=0xc0801000
+CONFIG_SPL_BSS_START_ADDR=0xc0851000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SYS_BOOTM_LEN=0xa000000
CONFIG_SYS_LOAD_ADDR=0x102000000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd4017000
CONFIG_DEBUG_UART_CLOCK=14700000
CONFIG_TARGET_SPACEMIT_K3=y
@@ -17,14 +26,20 @@ CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
CONFIG_RISCV_ISA_ZICBOM=y
+# CONFIG_SPL_SMP is not set
CONFIG_STACK_SIZE=0x100000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
# CONFIG_BOARD_INIT is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_RESET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_TLV_EEPROM=y
+CONFIG_SPL_CMD_TLV_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
@@ -47,6 +62,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_LWIP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_SPACEMIT=y
CONFIG_CLK_SPACEMIT_K3=y
CONFIG_SPACEMIT_GPIO=y
@@ -54,6 +71,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_SPACEMIT_K1=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
@@ -69,6 +87,9 @@ CONFIG_PMIC_SPACEMIT_P1=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_SPACEMIT_P1=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_SPL_SPACEMIT_K3_DDR=y
CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
@@ -77,3 +98,4 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_TIMER_EARLY=y
+CONFIG_SPL_LIB_RATIONAL=y
--
2.56.0
