Hi Junhui,
On 00:40 Fri 06 Nov , Junhui Liu wrote:
> Add the DDR controller node and mark the UART, I2C EEPROM and required
> clock and reset providers for use before DRAM initialization.
>
> Add a binman description for spl/u-boot-spl-mkimage.bin, combining SPL
> with the external LPDDR5 PMU IMEM firmware and wrapping the payload in
> a SpacemiT K3 boot image header.
>
> Signed-off-by: Junhui Liu <[email protected]>
> ---
> arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +++++++++++++++
> arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54
> ++++++++++++++++++++++++++++++++++
> 2 files changed, 78 insertions(+)
>
..
> diff --git a/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> index 352e85e7de8..0976b2647b5 100644
> --- a/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> +++ b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> @@ -4,3 +4,57 @@
> */
>
> #include "spacemit-k3-binman.dtsi"
> +
> +&{/soc} {
> + ddrc@cb000000 {
> + compatible = "spacemit,k3-ddrc";
> + reg = <0x0 0xcb000000 0x0 0x01000000>,
> + <0x0 0xcc000000 0x0 0x01000000>;
> + spacemit,apmu = <&syscon_apmu 0x4e8>;
> + bootph-pre-ram;
> + };
> +};
> +
I'm not sure if it's a good idea to also move "ddrc" to mainline kernel
dts, at least to reach a consensus about stable compatible name..
> +&i2c2 {
> + bootph-pre-ram;
> +
> + eeprom@50 {
> + bootph-pre-ram;
> + };
> +};
> +
For adding all "bootph-pre-ram" properties, I'd like to see patch
submission to mainline kernel tree, see similar thread for K1 SoC[1]
so eventually it will get synced to a proper directory under dts/upstream/..
But, I know it would take long time for the upstream dts hit into U-Boot
tree, so a compromised solution is that we temporarily accept this patch
before the sync, then fix it up later accordingly..
Link: https://lore.kernel.org/r/[email protected]
[1]
--
Yixun Lan (dlan)
