On Wed, Aug 22, 2018 at 5:32 PM Jason Matusiak < ja...@gardettoengineering.com> wrote:
> Brian, I really only want to send data when appropriate. I don't have the > code in front if me at the moment, but I can have tvalid high while I wait > for tready, right. So I don't see why it would be an issue if I change > tdata while tvalid is high and tready is low. > Changing tdata after tvalid was asserted while tready is low is a violation of the AXI4 streaming spec I am pretty sure. Don't do this. > > But I've spent the last two days trying to debuf this before I found out > it was the axi fifo filling up. It is weird to me that it is slowly falling > behind. It makes me feel like tlast maybe has something to do with it..... > The computation clock for the rfnoc blocks is around 214MHz. The radio sends stuff out at 200MHz, so you will always produce more and faster than the radio can keep up naturally. It's inherent in the system. Are you saying you are producing samples which should have gone out of the radio by the time you're making more, and the downstream FIFO's are not cleared out? This is a different problem altogether. I guess, if you can go back to the beginning, what exactly is happening that you are not sure about? Did you find this out using just simulation, or did you instrument an ILA inside the FPGA and are observing actual signals in the FPGA showing this phenomenon? Sorry for the confusion, but I think I misunderstood your original issue. Clarification is good to have. Brian >
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